We evaluate the applicability of many-core architectures for the simulation of networks on chips (NoC). Compared to the well established shared memory multi-core architectures, many-core architectures significantly di...
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ISBN:
(纸本)9781467387767
We evaluate the applicability of many-core architectures for the simulation of networks on chips (NoC). Compared to the well established shared memory multi-core architectures, many-core architectures significantly differ not only in the number of processing elements but also in the on-chip communication architecture, the memory subsystem, and the computational performance of an individual core. Proven multi-core simulation approaches do not consider such architectural aspects and thus suffer limited performance when being applied to many-core architectures. To enable high performance simulation, we identify conceptual drawbacks of state of the art parallel simulation approaches and consequently propose a novel globally asynchronous locally synchronous (GALS) simulation concept suited for many core architectures. Our results show that our GALS simulation approach yields a speedup of up to 2.3 over parallel discrete event simulation.
Accumulated cost surfaces (ACSs) are a tool for spatial modelling used in a number of fields. Some relevant. applications, especially in the areas of multi-criteria evaluation and spatial optimization, require the ava...
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ISBN:
(纸本)9781467387767
Accumulated cost surfaces (ACSs) are a tool for spatial modelling used in a number of fields. Some relevant. applications, especially in the areas of multi-criteria evaluation and spatial optimization, require the availability of several ACSs on the same raster, which may result in a significant computational cost. In this paper, we discuss some techniques available in the literature for accelerating the ACS computation using graphics processing units (GPUs) and CUDA. Also, we illustrate in details a new CUDA algorithm suitable for the computation of multiple ACSs. Moreover, we present some preliminary results on a test case, including an experimental comparison against a fast sequential implementation running on a CPU.
Emerging nanoscale silicon-photonics with its advances in fabrication and integration of on-chip CMOS-compatible optical elements are good news for system designers. Optical network-on-Chips (ONoCs) could be the next ...
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ISBN:
(纸本)9781467387767
Emerging nanoscale silicon-photonics with its advances in fabrication and integration of on-chip CMOS-compatible optical elements are good news for system designers. Optical network-on-Chips (ONoCs) could be the next generation of NoCs. On the other hand, hybrid opto-electrical networks may provide higher bandwidth, lower latency and better power dissipation when considering both optical and electrical characteristics on multicore platforms. the cluster based technique locally connects processing cores through electrical interconnect, while the clusters themselves are connected together through an optical waveguide. the experimental results show that in most benchmark applications, the cluster size of 4 proves to be an appropriate size for optimizing the energy-delay product (EDP) parameter.
We report on the analysis of gen_server, a popular Erlang library to build client-server applications. Our analysis uses a tool based on choreographic models. We discuss how, once the library has been modelled in term...
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ISBN:
(纸本)9781467387767
We report on the analysis of gen_server, a popular Erlang library to build client-server applications. Our analysis uses a tool based on choreographic models. We discuss how, once the library has been modelled in terms of communicating finite state machines, an automated analysis can be used to detect potential communication errors. the results of our analysis suggest how to properly use gen_server in order to guarantee the absence of communication errors.
this paper demonstrates on speeding up an accurate analysis of fault trees using stochastic logic through GPGPUs. Actually, probability models of dynamic gates and new accurate models for different combinations of col...
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ISBN:
(纸本)9781467387767
this paper demonstrates on speeding up an accurate analysis of fault trees using stochastic logic through GPGPUs. Actually, probability models of dynamic gates and new accurate models for different combinations of cold spare gate e.g., two cold spare gates with a share spare and a cold spare gate with more than one spare inputs are developed in this paper. Experimental results show that on average;the proposed analysis method is 235 times faster than CPU simulation time. Moreover, proposing new stochastic models results accuracy and simplicity as additional advantages of the proposed method.
From information security point of view embedded devices are the elements of complex systems operating in a potentially hostile environment. therefore development of embedded devices is a complex task that often requi...
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ISBN:
(纸本)9781467387767
From information security point of view embedded devices are the elements of complex systems operating in a potentially hostile environment. therefore development of embedded devices is a complex task that often requires expert solutions. the complexity of the task of developing secure embedded devices is caused by various types of threats and attacks that may affect the device, as well as that in practice security of embedded devices is usually considered at the final stage of the development process in the form of adding additional security features. the paper proposes a design technique and its application that will facilitate development of secure and energy efficient embedded devices. the technique organizes the search for the best combinations of security components on the basis of solving an optimization problem. the efficiency of the proposed technique is demonstrated by development of a room perimeter protection system.
Although the research on Internet of things (IoT) is emerging and getting popular, there are few mobile operators that offer connectivity services for IoT devices such as robots in their networks. One of the reasons i...
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ISBN:
(纸本)9783319571867;9783319571850
Although the research on Internet of things (IoT) is emerging and getting popular, there are few mobile operators that offer connectivity services for IoT devices such as robots in their networks. One of the reasons is security. Mobile operators who offer connectivity to IoT devices could benefit from an orchestrated security platform by applying data mining and classification based on the data collected to offer more reactive security notifications to owners of robots. For this purpose, we propose a distributed security platform for Mobile Cloud Robot (MCR) to detect and prevent an attack on the mobile network and robots based on the collected information from robots. the proposed platform includes robots, Local Robot Controller (LRC), Mobile Cloud, an IoT anomaly detection module and IoT orchestrator. this platform applies an orchestrated data analysis not only to achieve an accurate anomaly detection for robot security but also improves different aspects such as energy saving, processing time, fault detection etc.
Stereo matching techniques aim at reconstructing disparity maps from a pair of images. the use of stereo matching techniques in embedded systems is very challenging due to the complexity of the state-of-the-art algori...
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ISBN:
(纸本)9781467387767
Stereo matching techniques aim at reconstructing disparity maps from a pair of images. the use of stereo matching techniques in embedded systems is very challenging due to the complexity of the state-of-the-art algorithms. Local stereo matching algorithms are efficiently implemented on GPU [1] and DSP [2]. this paper presents the optimization of the One Dimension Belief Propagation (BP-1D) algorithm. BP-1D is faster than previous algorithms on monocore DSP [2] and its implementation onto multicore DSPs is straightforward. BP-1D implemented on multicore embedded platforms outperforms previous stereo matching implementations reaching real-time performances for resolutions up to 1080p with a 10 Watts power consumption.
the costs of current data centers are mostly driven by their energy consumption (specifically by the air conditioning, computing and networking infrastructure). Yet, current pricing models are usually static and rarel...
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ISBN:
(纸本)9781467387767
the costs of current data centers are mostly driven by their energy consumption (specifically by the air conditioning, computing and networking infrastructure). Yet, current pricing models are usually static and rarely consider the facilities' energy consumption per user. the challenge is to provide a fair and predictable model to attribute the overall energy costs per virtual machine (VM). Current pay-as-you-go models of Cloud providers allow users to easily know how much their computing will cost. However, this model is not fully transparent as to where the costs come from (e.g., energy). In this paper we introduce EPAVE, a model for Energy-Proportional Accounting in VM-based Environments. EPAVE allows transparent, reproducible and predictive cost calculation for users and for Cloud providers. We show these characteristics of EPAVE by a number of use cases in heterogeneous data centers and discuss the applicability of EPAVE.
In this paper, a throughput-aware transient fault detection method is presented with respect to the features of server processors. the proposed method takes the advantages of combination of reconfigurable redundant ex...
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ISBN:
(纸本)9781467387767
In this paper, a throughput-aware transient fault detection method is presented with respect to the features of server processors. the proposed method takes the advantages of combination of reconfigurable redundant execution-based fault detection and speculative fault detection. the reconfigurable redundant execution-based fault detection method by using configuration manager module couples two free adjacent cores on which a thread will be executed, and decouples them when resources are limited for normal execution. this method exploits unused resources in the multi core processors to ensure high throughput reliable execution. the speculative fault detection method uses a history of block addresses requested form L1 cache to L2 cache during thread execution to find abnormal execution behavior. In order to evaluate the proposed method, the alpha processor model is utilized in the context of Gem5 simulator. the experimental results showed that 70% of injected faults can be detected with negligible hardware overhead.
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