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Creating Cylindrical Panoramic Mosaic from a Pipeline Video

Creating Cylindrical Panoramic Mosaic from a Pipeline Video

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IEEE international conference on computer-aided design and computer graphics

作者： Chuan Niu Fan Zhong Songhua Xu Chenglei Yang Xueying Qin School of Computer Science and Technology Shandong Provincial Key Laboratory of Software Engineering Shandong University Jinan China Oak Ridge National Laboratory Oak Ridge TN USA

In geological engineering, stratum structure detection is a fundamental problem in project planning and implementation. One of the most commonly employed detection technologies is to take videos of borehole using a forward moving camera. Following this approach, the problem of stratum structure detection is transformed into the problem of constructing a panoramic image from the taken video sequences, which are typically in low quality. In this paper, we propose a novel method to create a panoramic image of the borehole from the video sequence without camera calibration and tracking. To stitch together pixels of neighboring frame images, our camera model is designed with a focal length changing feature, along with a small rotation freedom in the two-dimensional image space. Essentially, our camera model assumes target objects lie on a cylindrical wall and the camera moves forward along the central axis of the cylindrical wall. Our method robustly resolves these two degrees-of-freedoms through KLT feature tracking and constructs a panoramic image by stitching strips. Experiment results show that our method could efficiently generate high-quality panoramas for very long video sequences.

关键词： Cameras Strips Video sequences Solid modeling Geology Optical imaging Optical distortion

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Boolean satisfiability algorithms and applications in electronic design automation 12th

Boolean satisfiability algorithms and applications in electr...

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12th international conference on computer aided Verification, CAV 2000

作者： Marques-Silva, João Sakallah, Karem R. Alves Redol 9 Lisboa1000-029 Portugal The University of Michigan Ann ArborMI48109-2122 United States

ISBN: (纸本)3540677704

Boolean Satisfiability (SAT) is often used as the underlying model for a significant and increasing number of applications in Electronic design Automation (EDA) as well as in many other fields of computer Science and Engineering. In recent years, new and efficient algorithms for SAT have been developed, allowing much larger problem instances to be solved. SAT "packages" are currently expected to have an impact on EDA applications similar to that of BDD packages since their introduction more than a decade ago. this tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem. Specifically, we highlight the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation, among others. In addition, we provide an overview of the algorithmic techniques commonly used for solving SAT, including those that have seen widespread use in specific EDA applications. We categorize these algorithmic techniques, indicating which have been shown to be best suited for which tasks. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Model checking

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Liveness and acceleration in parameterized verification 12th

Liveness and acceleration in parameterized verification

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12th international conference on computer aided Verification, CAV 2000

作者： Pnueli, Amir Shahar, Elad Dept. of Computer Science and Applied Mathematics Weizmann Institute of Science Rehovot Israel

ISBN: (纸本)3540677704

the paper considers the problem of uniform verification of parameterized systems by symbolic model checking, using formulas in FS1S (a syntactic variant of the 2nd order logic WS1S) for the symbolic representation of sets of states. the technical difficulty addressed in this work is that, in many cases, standard model-checking computations fail to converge. Using the tool TLV[P], we formulated a general approach to the acceleration of the transition relations, allowing an unbounded number of different processes to change their local state (or interact with their neighbor) in a single step. We demonstrate that this acceleration process solves the difficulty and enables an efficient symbolic model-checking of many parameterized systems such as mutual-exclusion and token-passing protocols for any value of N, the parameter specifying the size of the system. Most previous approaches to the uniform verification of parameterized systems, only considered safety properties of such systems. In this paper, we present an approach to the verification of iveness properties and demonstrate its application to prove accessibility properties of the considered protocols. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Acceleration

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Regular model checking 12th

Regular model checking

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12th international conference on computer aided Verification, CAV 2000

作者： Bouajjani, Ahmed Jonsson, Bengt Nilsson, Marcus Touili, Tayssir Liafa Univ. Paris 7 Case 7014 2 place Jussieu Paris Cedex 0575251 France Dept. of Computer Systems P.O. Box 325 UppsalaS-751 05 Sweden

ISBN: (纸本)3540677704

We present regular model checking, a framework for algorithmic verification of infinite-state systems with, e.g., queues, stacks, integers, or a parameterized linear topology. States are represented by strings over a finite alphabet and the transition relation by a regular length-preserving relation on strings. Major problems in the verification of parameterized and infinite-state systems are to compute the set of states that are reachable from some set of initial states, and to compute the transitive closure of the transition relation. We present two complementary techniques for these problems. One is a direct automata-theoretic construction, and the other is based on widening. Both techniques are incomplete in general, but we give sufficient conditions under which they work. We also present a method for verifying ω-regular properties of parameterized systems, by computation of the transitive closure of a transition relation. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Model checking

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XMC: A logic-programming-based verification toolset 12th

XMC: A logic-programming-based verification toolset

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12th international conference on computer aided Verification, CAV 2000

作者： Ramakrishnan, C.R. Ramakrishnan, I.V. Smolka, Scott A. Dong, Yifei Du, Xiaoqun Roychoudhury, Abhik Venkatakrishnan, V.N. Department of Computer Science SUNY at Stony Brook Stony BrookNY11794-4400 United States

ISBN: (纸本)3540677704

XMC is a toolset for specifying and verifying concurrent systems. Its main mode of verification is temporal-logic model checking [CES86], although equivalence checkers have also been implemented. In its current form, temporal properties are specified in the alternation-free fragment of the modal mu-calculus [Koz83], and system models are specified in XL, a value-passing language based on CCS [Mil89]. the core computational components of the XMC system, such as those for compiling the specification language, model checking, etc., are built on top of the XSB tabled logic-programming system [XSB99].

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Verifying advanced microarchitectures that support speculation and exceptions 12th

Verifying advanced microarchitectures that support speculati...

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12th international conference on computer aided Verification, CAV 2000

作者： Hosabettu, Ravi Gopalakrishnan, Ganesh Srivas, Mandayam Department of Computer Science University of Utah Salt Lake CityUT84112 United States Computer Science Laboratory SRI International Menlo ParkCA94025 United States

ISBN: (纸本)3540677704

In this paper, we discuss the verification of a microprocessor involving a reorder buffer, a store buffer, speculative execution and exceptions at the microarchitectural level. We extend the earlier proposed Completion Functions Approach [HSG98] in a uniform manner to handle the verification of such microarchitectures. the key extension to our previous work was in systematically extending the abstraction map to accommodate the possibility of all the pending instructions being squashed. An interesting detail that arises in doing so is how the commutativity obligation for the program counter is proved despite the program counter being updated by both the instruction fetch stage (when a speculative branch may be entertained) and the retirement stage (when the speculation may be discovered to be incorrect). Another interesting detail pertains to how store buffers are handled. We highlight a new type of invariant in this work-one which keeps correspondence between store buffer pointers and reorder buffer pointers. All these results, taken together with the features handled using the completion functions approach in our earlier published work [HSG98,HSG99,HGS99], demonstrates that the approach is uniformly applicable to a wide variety of pipelined designs. © Springer-Verlag Berlin Heidelberg 2000.

关键词： computer architecture

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Model checking continuous-Time Markov chains by transient analysis 12th

Model checking continuous-Time Markov chains by transient an...

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12th international conference on computer aided Verification, CAV 2000

作者： Baier, Christel Haverkort, Boudewijn Hermanns, Holger Katoen, Joost-Pieter Institut für Informatik I University of Bonn Römerstraße 164 BonnD-53117 Germany Dept.of Computer Science RWTH Aachen Ahornstraße 55 AachenD-52056 Germany Dept.of Computer Science University of Twente P.O. Box 217 Enschede7500 AE Netherlands

ISBN: (纸本)3540677704

the verification of continuous-time Markov chains (CTMCs) against continuous stochastic logic (CSL) [3,6], a stochastic branchingtime temporal logic, is considered. CSL facilitates among others the specification of steady-state properties and the specification of probabilistic timing properties of the form P(image found)p(Φ1 UI Φ2), for state formulas Φ1 and Φ2, comparison operator (image found), probability p, and real interval I. the main result of this paper is that model checking probabilistic timing properties can be reduced to the problem of computing transient state probabilities for CTMCs. this allows us to verify such properties by using efficient techniques for transient analysis of CTMCs such as uniformisation. A second result is that a variant of ordinary lumping equivalence (i.e., bisimulation), a well-known notion for aggregating CTMCs, preserves the validity of all CSL-formulas. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Transient analysis

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A discrete strategy improvement algorithm for solving parity games 12th

A discrete strategy improvement algorithm for solving parity...

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12th international conference on computer aided Verification, CAV 2000

作者： Vöge, Jens Jurdziński, Marcin Lehrstuhl für Informatik VII RWTH Aachen AachenD-52056 Germany BRICS Department of Computer Science University of Århus Ny Munkegade Bldg. 540 Arhus CDK-8000 Denmark

ISBN: (纸本)3540677704

A discrete strategy improvement algorithm is given for constructing winning strategies in parity games, thereby providing also a new solution of the model-checking problem for the modal μ-calculus. Known strategy improvement algorithms, as proposed for stochastic games by Hoffman and Karp in 1966, and for discounted payoff games and parity games by Puri in 1995, work with real numbers and require solving linear programming instances involving high precision arithmetic. In the present algorithm for parity games these dificulties are avoided by the use of discrete vertex valuations in which information about the relevance of vertices and certain distances is coded. An efficient implementation is given for a strategy improvement step. Another advantage of the present approach is that it provides a better conceptual understanding and easier analysis of strategy improvement algorithms for parity games. However, so far it is not known whether the present algorithm works in polynomial time. the long standing problem whether parity games can be solved in polynomial time remains open. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Linear programming

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Binary reachability analysis of discrete pushdown timed automata 12th

Binary reachability analysis of discrete pushdown timed auto...

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12th international conference on computer aided Verification, CAV 2000

作者： Dang, Zhe Ibarra, Oscar H. Bultan, Tevfik Kemmerer, Richard A. Su, Jianwen Department of Computer Science University of California Santa BarbaraCA93106 United States

ISBN: (纸本)3540677704

We introduce discrete pushdown timed automata that are timed automata with integer-valued clocks augmented with a pushdown stack. A configuration of a discrete pushdown timed automaton includes a control state, finitely many clock values and a stack word. Using a pure automata-theoretic approach, we show that the binary reachability (i.e., the set of all pairs of configurations (α, β), encoded as strings, such that α can reach β through 0 or more transitions) can be accepted by a nondeterministic pushdown machine augmented with reversal-bounded counters (NPCM). Since discrete timed automata with integer-valued clocks can be treated as discrete pushdown timed automata without the pushdown stack, we can show that the binary reachability of a discrete timed automaton can be accepted by a nondeterministic reversal-bounded multi-counter machine. thus, the binary reachability is Presburger. By using the known fact that the emptiness problem is decidable for reversal- bounded NPCMs, the results can be used to verify a number of properties that cannot be expressed by timed temporal logics for discrete timed automata and CTL* for pushdown systems. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Clocks

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Detecting errors before reaching them 12th

Detecting errors before reaching them

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12th international conference on computer aided Verification, CAV 2000

作者： De Alfaro, Luca Henzinger, thomas A. Mang, Freddy Y. C. Department of Electrical Engineering and Computer Sciences University of California at Berkeley CA94720-1770 United States

ISBN: (纸本)3540677704

Any formal method or tool is almost certainly more often applied in situations where the outcome is failure (a counterexample) rat- her than success (a correctness proof). We present a method for symbolic model checking that can lead to significant time and memory savings for model-checking runs that fail, while occurring only a small overhead for model-checking runs that succeed. Our method discovers an error as soon as it cannot be prevented, which can be long before it actually occurs;for example, the violation of an invariant may become unpreventable many transitions before the invariant is violated. the key observation is that "unpreventability" is a local property of a single module: an error is unpreventable in a module state if no environment can prevent it. therefore, unpreventability is inexpensive to compute for each module, yet can save much work in the state exploration of the global, compound system. Based on different degrees of information available about the environment, we define and implement several notions of "unpreventability," including the standard notion of uncontrollability from discrete-event control. We present experimental results for two examples, a distributed database protocol and a wireless communication protocol. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Model checking

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