Compositional real-time scheduling frameworks provide ways for building large and complex real-timeembeddedsystems from independent sub-systems. this paper introduces a novel scheme for scheduling a component of Mix...
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ISBN:
(纸本)9781479950799
Compositional real-time scheduling frameworks provide ways for building large and complex real-timeembeddedsystems from independent sub-systems. this paper introduces a novel scheme for scheduling a component of Mixed-Criticality (MC) sporadic tasks on uniprocessor system. It characterizes the mixed criticality resource allocations, and the interface model for abstracting the real-time requirements of such a component. the demand bound function and supply bound function for the low and high criticality modes are derived to determine the schedulability of a component in both modes. the execution times of jobs are monitored in this approach. If it is detected that the behavior of system is inconsistent with low criticality level, then tasks of low criticalities are discarded and the priorities of high criticality tasks are re-ordered in high criticality mode to guarantee the schedulabilty of high criticality tasks. We propose a new algorithm, which schedules a component of mixed criticality jobs in low mode through MC Rate Monotonic (MC-RM) algorithm by applying period transformation, and guarantees the schedulabilty by using MC Earliest Deadline First (MC-EDF) algorithm in high mode.
the usage of caches in multi-and many-core systems for timing critical applications is a challenging issue. time-predictability shaped up as the essential characteristic of a cache when talking about the suitability f...
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ISBN:
(纸本)9780769550220
the usage of caches in multi-and many-core systems for timing critical applications is a challenging issue. time-predictability shaped up as the essential characteristic of a cache when talking about the suitability for hard real-timesystems. Common cache coherence mechanisms corrupt the timing analysability of a cache memory because of unpredictable interferences between the caches. thus, these mechanisms are unsuitable for hard real-timesystems. In this work, we briefly describe the ODC2 together with an extension which increases the cache hit rate. We evaluated the performance of the extended ODC2 by comparing it to analysable uncached accesses to shared data and to the well-known but unpredictable MESI and MOESI coherence techniques.
the importance of accounting for interrupts in multiprocessor real-time schedulability analsysis is discussed: three interrupt accounting methods, two of which are newly described here, are analyzed and compared.
ISBN:
(纸本)9780769537870
the importance of accounting for interrupts in multiprocessor real-time schedulability analsysis is discussed: three interrupt accounting methods, two of which are newly described here, are analyzed and compared.
Securing communication sessions between networked embeddedsystems is a major challenge that needs to be addressed as an increasing number of such systems become Internet-enabled. Securely and quickly establishing a s...
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ISBN:
(纸本)0769526764
Securing communication sessions between networked embeddedsystems is a major challenge that needs to be addressed as an increasing number of such systems become Internet-enabled. Securely and quickly establishing a session key between communicating nodes in a network requires authentication of node identities. In this paper, we propose a simple elliptic-curve based key negotiation protocol suitable for fully hardware implementation as a protocol on chip (PoC). the protocol uses the elliptic curve variants of boththe Diffie Hellmann exchange and the Digital Signature Algorithm. Timing results demonstrate that an end-to-end protocol run can be performed in as little as 28ms on a 25MHz clock, which is several times faster than previous microprocessor-based implementations of similar protocols. the results indicate that session keys can thereby have shorter lifetimes, since there is little computational overhead in re-generating them, thus enhancing overall security of the networked embeddedsystems.
In this paper, we are interested in the energy-efficient scheduling of real-time tasks which may access lock-free objects in a non-ideal DVS processor. We propose an algorithm, called interference-aware speed assignme...
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ISBN:
(纸本)9781479950799
In this paper, we are interested in the energy-efficient scheduling of real-time tasks which may access lock-free objects in a non-ideal DVS processor. We propose an algorithm, called interference-aware speed assignment (IASA), to assign proper execution speeds to tasks which are scheduled by the earliest deadline first (EDF) scheduling policy. the execution speeds are calculated based on the schedulability analysis of the EDF policy withthe cost of lock-free objects' retry loops. As a result, the energy consumption can be reduced while satisfying the timing constraints of real-time tasks. Our experimental results show that the IASA algorithm is very effective in energy saving.
In this paper, we show how code can be generated at different levels of abstraction from a single source description. To this end, we use a model-driven development tool called Averest that is based on a synchronous p...
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ISBN:
(纸本)9781479908516
In this paper, we show how code can be generated at different levels of abstraction from a single source description. To this end, we use a model-driven development tool called Averest that is based on a synchronous programming language. We illustrate our approach by means of a case study from the domain of distributed real-time automotive embeddedsystems. this paper focuses thereby mainly on the use of the Averest toolkit to generate code at different levels of abstraction.
It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-timeapplications. the effectiveness comes from the fact that the amount of energy co...
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ISBN:
(纸本)0769526764
It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-timeapplications. the effectiveness comes from the fact that the amount of energy consumption is quadractically proportional to the voltage applied to the processor the penalty is the execution delay, which is linearly and inversely proportional to the voltage. According to the granularity of units to which voltage scaling is applied, the DVS problem is divided into two subproblems: inter-task DVS problem, in which the determination of the voltage is carried out on a task-by-task basis and the voltage assigned to the task is unchanged during the whole execution of the task, and intra-task DVS problem, in which the operating voltage of a task is dynamically adjusted according to the execution behavior to reflect the changes of the required number of cycles to finish the task before the deadline. Frequent voltage transitions may cause an adverse effect on energy minimizatuion due to the increase of the overhead of transition time and energy. In this paper, we survey and describe, in a theoretical aspect, state-of-art techniques of dynamic voltage scaling problems, which include: (1) inter-task DVS problem, (2) intra-task DVS problem, (3) integrated inter-task and intra-task DVS-problem, and (4) transition-aware DVS problem.
As real-timeembeddedsystems demand more and more computing power under reasonable energy budgets, multi-core platforms are a viable option. However, deploying real-timeapplications on multi-core platforms introduce...
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ISBN:
(纸本)9781479989379
As real-timeembeddedsystems demand more and more computing power under reasonable energy budgets, multi-core platforms are a viable option. However, deploying real-timeapplications on multi-core platforms introduce several predictability challenges. One of these challenges is bounding the latency of memory accesses issued by real-time tasks. this challenge is exacerbated as the number of cores and, hence, the degree of resource sharing increases. Over the last several years, researchers have proposed techniques to overcome this challenge. In prior work, we proposed an arbitration policy for memory access requests over a Network-on-Chip. In this paper, we implement and evaluate variants of our arbitration policy on a real hardware platform, namely Tilera's TilePro64 platform.
Multi-core platforms are becoming the dominant computing architecture for next generation embeddedsystems. Nevertheless, designing, programming, and analyzing such systems is not easy and a solid methodology is still...
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ISBN:
(纸本)9780769537870
Multi-core platforms are becoming the dominant computing architecture for next generation embeddedsystems. Nevertheless, designing, programming, and analyzing such systems is not easy and a solid methodology is still missing. In this paper, we propose two powerful abstractions to model the computing power of a parallel machine, which provide a general interface for developing and analyzing real-timeapplications in isolation, independently of the physical platform. the proposed abstractions can be applied on top of different types of service mechanisms, such as periodic servers, static partitions, and P-fair time partitions. In addition, we developed the schedulability analysis of a set of real-time tasks on top of a parallel machine that is compliant withthe proposed abstractions.
Soft real-time sporadic multiprocessor task systems are considered that include processing pipelines. Conditions are presented for guaranteeing bounded deadline tardiness in such systems under global EDF or FIFO sched...
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ISBN:
(纸本)9780769537870
Soft real-time sporadic multiprocessor task systems are considered that include processing pipelines. Conditions are presented for guaranteeing bounded deadline tardiness in such systems under global EDF or FIFO scheduling. "Early-releasing" is applied to make pipeline scheduling work-conserving. this lessens job response times in lightly-loaded systems.
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