Utilization bounds for Earliest Deadline First(EDF) and Rate Monotonic(RM) scheduling are known and well understood for uniprocessor systems. In this paper, we derive limits on similar bounds for the multiprocessor ca...
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ISBN:
(纸本)0769526764
Utilization bounds for Earliest Deadline First(EDF) and Rate Monotonic(RM) scheduling are known and well understood for uniprocessor systems. In this paper, we derive limits on similar bounds for the multiprocessor case, when the individual processors need not be identical. Tasks are partitioned among the processors and RM scheduling is assumed to be the policy used in individual processors. A minimum limit on the bounds for a 'greedy' class of algorithms is given and proved, since the actual value of the bound depends on the algorithm that allocates the tasks. We also derive the utilization bound of an algorithm which allocates tasks in decreasing order of utilization factors. Knowledge of such bounds allows us to carry out very fast schedulability tests although we are constrained by the fact that the tests are sufficient but not necessary to ensure schedulability.
the importance of accounting for interrupts in multiprocessor real-time schedulability analsysis is discussed: three interrupt accounting methods, two of which are newly described here, are analyzed and compared.
ISBN:
(纸本)9780769537870
the importance of accounting for interrupts in multiprocessor real-time schedulability analsysis is discussed: three interrupt accounting methods, two of which are newly described here, are analyzed and compared.
real-time database system must meet time constraints in addition to the integrity constraints. Concurrency control is one of the main issues in the studies of real-time database systems. Traditional concurrency contro...
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In this paper we address the "rate analysis" problem for media-processing platforms consisting of multiple processor cores connected in a pipelined fashion. More precisely, we aim at determining tight bounds...
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ISBN:
(纸本)0769526764
In this paper we address the "rate analysis" problem for media-processing platforms consisting of multiple processor cores connected in a pipelined fashion. More precisely, we aim at determining tight bounds on the rates at which multimedia streams can be fed into such architectures. these bounds depend on architectural constraints (e.g. the available on-chip memory, bus arbitration policies, etc.), as well as the application characteristics (e.g. application partitioning and mapping, workload rates generated by different tasks, etc.). the proposed framework for rate analysis can be used for fast design space exploration to determine how these bounds change with different architectural parameters, mapping of the application, or changing the QoS requirements associated withthe input streams.
In this paper, we show how code can be generated at different levels of abstraction from a single source description. To this end, we use a model-driven development tool called Averest that is based on a synchronous p...
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ISBN:
(纸本)9781479908516
In this paper, we show how code can be generated at different levels of abstraction from a single source description. To this end, we use a model-driven development tool called Averest that is based on a synchronous programming language. We illustrate our approach by means of a case study from the domain of distributed real-time automotive embeddedsystems. this paper focuses thereby mainly on the use of the Averest toolkit to generate code at different levels of abstraction.
the usage of caches in multi-and many-core systems for timing critical applications is a challenging issue. time-predictability shaped up as the essential characteristic of a cache when talking about the suitability f...
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ISBN:
(纸本)9780769550220
the usage of caches in multi-and many-core systems for timing critical applications is a challenging issue. time-predictability shaped up as the essential characteristic of a cache when talking about the suitability for hard real-timesystems. Common cache coherence mechanisms corrupt the timing analysability of a cache memory because of unpredictable interferences between the caches. thus, these mechanisms are unsuitable for hard real-timesystems. In this work, we briefly describe the ODC2 together with an extension which increases the cache hit rate. We evaluated the performance of the extended ODC2 by comparing it to analysable uncached accesses to shared data and to the well-known but unpredictable MESI and MOESI coherence techniques.
In this paper, we are interested in the energy-efficient scheduling of real-time tasks which may access lock-free objects in a non-ideal DVS processor. We propose an algorithm, called interference-aware speed assignme...
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ISBN:
(纸本)9781479950799
In this paper, we are interested in the energy-efficient scheduling of real-time tasks which may access lock-free objects in a non-ideal DVS processor. We propose an algorithm, called interference-aware speed assignment (IASA), to assign proper execution speeds to tasks which are scheduled by the earliest deadline first (EDF) scheduling policy. the execution speeds are calculated based on the schedulability analysis of the EDF policy withthe cost of lock-free objects' retry loops. As a result, the energy consumption can be reduced while satisfying the timing constraints of real-time tasks. Our experimental results show that the IASA algorithm is very effective in energy saving.
Marte (A UML Profilefor Modeling and Analysis of real-time and embeddedsystems) is a new UML profile extension for real-time and embeddedsystems, which is going to be standardized by mid 2007 at OMG (Object Manageme...
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ISBN:
(纸本)9780769528953
Marte (A UML Profilefor Modeling and Analysis of real-time and embeddedsystems) is a new UML profile extension for real-time and embeddedsystems, which is going to be standardized by mid 2007 at OMG (Object Management Group). this standard has been proposed by the "ProMarte" consortium, which consists of OMG end-users, tool providers and academics. Marte defines concepts in terms of UML extensions needed to model and analyze real-time and embeddedsystems (R TIES). the Marte specification provides an annex which handles its relation to AADL-based models, and the way it may represent them.. Our purpose in this paper is to describe this relation. Our constructions will be presented and illustrated through some examples.
It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-timeapplications. the effectiveness comes from the fact that the amount of energy co...
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ISBN:
(纸本)0769526764
It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-timeapplications. the effectiveness comes from the fact that the amount of energy consumption is quadractically proportional to the voltage applied to the processor the penalty is the execution delay, which is linearly and inversely proportional to the voltage. According to the granularity of units to which voltage scaling is applied, the DVS problem is divided into two subproblems: inter-task DVS problem, in which the determination of the voltage is carried out on a task-by-task basis and the voltage assigned to the task is unchanged during the whole execution of the task, and intra-task DVS problem, in which the operating voltage of a task is dynamically adjusted according to the execution behavior to reflect the changes of the required number of cycles to finish the task before the deadline. Frequent voltage transitions may cause an adverse effect on energy minimizatuion due to the increase of the overhead of transition time and energy. In this paper, we survey and describe, in a theoretical aspect, state-of-art techniques of dynamic voltage scaling problems, which include: (1) inter-task DVS problem, (2) intra-task DVS problem, (3) integrated inter-task and intra-task DVS-problem, and (4) transition-aware DVS problem.
As real-timeembeddedsystems demand more and more computing power under reasonable energy budgets, multi-core platforms are a viable option. However, deploying real-timeapplications on multi-core platforms introduce...
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ISBN:
(纸本)9781479989379
As real-timeembeddedsystems demand more and more computing power under reasonable energy budgets, multi-core platforms are a viable option. However, deploying real-timeapplications on multi-core platforms introduce several predictability challenges. One of these challenges is bounding the latency of memory accesses issued by real-time tasks. this challenge is exacerbated as the number of cores and, hence, the degree of resource sharing increases. Over the last several years, researchers have proposed techniques to overcome this challenge. In prior work, we proposed an arbitration policy for memory access requests over a Network-on-Chip. In this paper, we implement and evaluate variants of our arbitration policy on a real hardware platform, namely Tilera's TilePro64 platform.
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