An embeddedreal-time system consists of a number of components (processes) that run concurrently and communicate with each other under predefined tinting constraints. the correctness of such systems is important, sin...
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ISBN:
(纸本)0769509304
An embeddedreal-time system consists of a number of components (processes) that run concurrently and communicate with each other under predefined tinting constraints. the correctness of such systems is important, since they are used in an increasing number of safety critical systems. To improve the quality of these systems, two techniques can be used, namely verification of the specification and testing of the implementation. III this paper;we consider the testing of embeddedreal-time components. In our model, the system is modeled as a set of Communicating timed Input Output Automata (CTIOA). One CTIOA specifies the component to be tested and the remaining CTIOAs represent the context. the relationship between the component to be rested and the other ones should be taken into account for test cases generation. We discuss how testing in contest differs from testing in isolation. We review the fault model in the context of CTIOA and we propose an approach for test cases generation from an embedded CTIOA. this approach consists of three steps. Fir st, we avoid the composition of all machines by selecting, based on a specific criterion, only some pal-ts of the CTIOA's contest that affect (or al-e affected by) the specification. then, we deter-mine the pal tial product of the specification and the selected pal-ts of the context. Finally: we apply timed Wp-Method [7] on the resulting rimed input output automata. the quality of the resulting pa, tial product is strongly dependent on the criterion used to select the parts of the contest to consider in test cases generation.
Execution time analysis is used in the development of real-time and embeddedsystems to dei-ive the timing estimates required for schedulability analysis. the execution time of the analyzed program is typically obtain...
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ISBN:
(纸本)0769509304
Execution time analysis is used in the development of real-time and embeddedsystems to dei-ive the timing estimates required for schedulability analysis. the execution time of the analyzed program is typically obtained by combining results from program flow analysis (such as number of iterations in loops) with low-level timing information. this paper proposes a method for low-level timing analysis based on measurements of execution times of programs executing on the actual target architecture. the essence of the method is to del-ive a system of linear equations fr om a limited number of timing measurements of an instrumented version of the considered program. the solution to these equations give execution times for program fragments, from which execution time measures for the entire program can be derived. the main advantage withthis approach is that architectural modeling is not needed, hence the risk of a discrepancy between model and real system is avoided. Also, compared to the non-exhaustive measurements performed in industry today, our approach is more structured and gives complete cover age in terms of the program paths considered. We present our method in the context of a simple, but reasonably realistic, processor model and show how it cart be extended to architectures with pipelines.
Proposes a framework to model fault-tolerant real-timesystems consisting of RobustRTOs (Robust real-time Objects) and RMOs (Region Monitor real-time Objects). A RobustRTO is an object which is capable of tolerating f...
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the proceedings contain 69 papers. the topics discussed include: schedulability-aware mapping of real-time object-oriented models to multi-threaded implementations;using measurements to derive the worst-case execution...
ISBN:
(纸本)0769509304
the proceedings contain 69 papers. the topics discussed include: schedulability-aware mapping of real-time object-oriented models to multi-threaded implementations;using measurements to derive the worst-case execution time;extracting safe and precise control flow from binaries;low-level analysis of a portable Java byte code WCET analysis framework;dynamic memory management for real-timeembedded Java chips;efficient pure-buffer algorithms for real-timesystems;a comparative study of the realization of rate-based computing services in general purpose operating systems;chopping and versioning real-time transactions to avoid remote blocking;efficient resource management for hard real-time communication over differentiated services architectures;minimizing the maximum end-to-end delay on tree structure using the distributed pinwheel model;and a multi-server design for a distributed mpeg video system with streaming support and QoS control.
this paper presents the SIMD Phase Programming Model, a simple approach to solving asynchronous, irregular problems on massively parallel SIMD computers. the novelty of this model consists of a simple, clear method on...
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ISBN:
(纸本)0769507166
this paper presents the SIMD Phase Programming Model, a simple approach to solving asynchronous, irregular problems on massively parallel SIMD computers. the novelty of this model consists of a simple, clear method on how to turn a general serial program into an explicitly parallel one for a SIMD machine, transferring a portion of the flow control into the single PEs. three case studies (the Mandelbrot Set, the N-Queen problem, and a Hopfield neural network that approximates the maximum clique in a graph) will be presented, implemented on two different SIMD computers (the UCSC Kestrel and the MasPar MP-2). Our results so far show good performance with respect to conventional serial CPU computingtime and in, terms of the high parallel speedup and efficiency achieved.
there is a trend for the information products that are integrated by computer, communication, and consumer electronics. the OS is required more compact and practical. An embedded system STARth is developed based on th...
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We present a tool for the design and validation of embeddedrealtimeapplications. the tool integrates two approaches: the use of the synchronous programming language, ESTEREL for design, and the application of model...
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We present a tool for the design and validation of embeddedrealtimeapplications. the tool integrates two approaches: the use of the synchronous programming language, ESTEREL for design, and the application of model checking techniques for validation of realtime properties. Validation is carried out on a global formal model (timed automata) taking into account the effective implementation of the application on the target hardware architecture as well as its external environment behavior.
the verification of software is more complex than hardware due to inherent flexibilities (dynamic behavior) that incur a multitude of possible system states. the verification of Concurrent embeddedreal-time Software ...
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the verification of software is more complex than hardware due to inherent flexibilities (dynamic behavior) that incur a multitude of possible system states. the verification of Concurrent embeddedreal-time Software (CERTS) is all the more difficult due to its concurrency and embeddedness. the work presented shows how the complexity of CERTS verification can be reduced significantly through answering common engineering questions such as when, where, and how one must verify embedded software. Application examples illustrate the usefulness of our technique in increasing verification scalability.
We study model checking problems for pushdown systems and linear time logics. We show that the global model checking problem (computingthe set of configurations, reachable or not, that violate the formula) can be sol...
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embeddedsystems have widespread use in consumer, commercial, and military applications. Reactive and real-time are two main characteristics of these systems. As one kind of real-timeembedded system, embedded digital...
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embeddedsystems have widespread use in consumer, commercial, and military applications. Reactive and real-time are two main characteristics of these systems. As one kind of real-timeembedded system, embedded digital signal processing (EDSP) systems use a special architecture to achieve better performance in DSP applications. Generally, there is no great difference between floating-point FFT and fixed-point FFT on general-purpose computer systems. However, in embedded DSP systems, the precision and range become the bottleneck of the performance of fixed-pointed FFT. In most cases, how to keep the balance of precision and real-time becomes a serious problem during the design phase of EDSP systems. We present a novel fixed-point FFT algorithm which can make designers easily adjust the precision and execution time of FFT. It is very useful to the co-design of EDSP systems. this paper also analyzes the novel algorithm from the viewpoint of round-off error analysis and presents the benchmarks on C6201.
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