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检索条件"任意字段=12th International Symposium on Parallel Architectures, Algorithms and Programming, PAAP 2021"

共 29 条记录，以下是11-20 订阅

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Efficient Algorithm for Home Care Scheduling with Budget Constraint

Efficient Algorithm for Home Care Scheduling with Budget Con...

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international symposium on parallel architectures, algorithms and programming (paap)

作者： Xinxuan Huang Jigang Wu Tonglai Liu Jinyao Huang School of Computer Science and Technology Guangdong University of Technology Guangzhou China College of Information Science and Technology Zhongkai University of Agriculture and Engineering Guangzhou China

ISBN: (纸本)9781665496407

Effective caregiver routing and scheduling methods can improve the service quality of home care and reduce operating costs. How to enable patients to obtain cost-effective home care services within a certain budget is a key issue. Few existing works take into account the patient's budget in home health care issues. therefore, we propose a new home care problem to minimize the route cost, which includes the weighted sum of total economic benefits, the dissatisfaction of patients and the travel time of caregivers, so as to ensure that caregivers can have satisfactory income and patients can obtain cost-effective services. A genetic algorithm (ARGA) customized with one crossover operation and six mutation operations is designed to solve this problem. Experimental results show that the algorithm ARGA can effectively reduce the route cost by 59.3%, 14.3% and 10.7% respectively, compared with the baselines BA, GA and TS.

关键词： Costs Medical services programming Search problems Routing Scheduling parallel architectures

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Accelerating a Lossy Compression Method with Fine-Grained parallelism on a GPU

Accelerating a Lossy Compression Method with Fine-Grained Pa...

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international symposium on parallel architectures, algorithms and programming (paap)

作者： Yifan Wu Jingcheng Shen Masao Okita Fumihiko Ino Graduate School of Information Science and Technology Osaka University Osaka Japan

ISBN: (纸本)9781665496407

With the rapid increase of data size processed by nowadays applications, high-performance compression methods become important to reduce both the memory consumption and the amount of data transfer. However, unlike the studies on CPU-based compression methods, those on GPU-based compression methods are insufficient. In this work, we target a lossy compression method that reported a high performance on a CPU-centric supercomputer. We propose schemes with fine-grained parallelism to accelerate the CPU-based method on the GPU, solving data dependency and write conflict issues in compression and decompression processes. Experimental results show that the proposed method achieved both higher performance, i.e., 42.0x and 1.9x speedups at best compared to the original method and a state-of-the-art GPU-based lossy compression method, respectively. Moreover, the proposed method achieved at best 1.2x and 1.8x as large as the compression ratio achieved by the original method and the state-of-the-art GPU-based lossy compression method, respectively.

关键词： Memory management Graphics processing units parallel processing programming Data transfer Supercomputers parallel architectures

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Vertex-Disjoint Paths in BCDC Networks

Vertex-Disjoint Paths in BCDC Networks

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international symposium on parallel architectures, algorithms and programming (paap)

作者： Xi Wang Jianxi Fan Suzhou Institute of Industrial Technology Suzhou China Key Laboratory of Symbolic Computation and Knowledge Engineering of Ministry of Education Jilin University Changchun P.R. China School of Computer Science and Technology Soochow University Suzhou China

ISBN: (纸本)9781665496407

For any integer $n\geq 2,\ B_{n}$ , the $n$ -dimensional BCDC network, based on a class of BC networks, crossed cube, is a server-centric and high-performance data center network for mega data centers with manageable cabling complexity. Implementing vertex-disjoint paths has great value of application in fault-tolerance and multi-path routing of data center networks. In this paper, we construct $n$ vertex-disjoint paths joining every two distinct vertices in $B_{n}$ , whose maximum length is limited by $\lceil\frac{n}{2}\rceil+5$ , where the diameter of $B_{n}$ is $\lceil\frac{n+1}{2}\rceil+1$ . Our results are fundamental and essential for fault-tolerance and multi-path routing in BCDC networks.

关键词： Data centers Fault tolerance Fault tolerant systems programming Routing parallel architectures Complexity theory

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Joint Optimization of Path Planning and Task Assignment for Space Robot

Joint Optimization of Path Planning and Task Assignment for ...

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international symposium on parallel architectures, algorithms and programming (paap)

作者： Yifei Sun Zikai Zhang Yidong Li Jigang Wu School of Computer Science and Technology Guangdong University of Technology Guangzhou China School of Computer and Information Technology Beijing Jiaotong University State Key Lab of Rail Traffic Control and Safety Beijing Jiaotong University

ISBN: (纸本)9781665496407

the space robot has been used widely in the aerospace industry. Because of the special working environment and limited fuel, an appropriate path is necessary for space robots to work. this paper investigates the path planning for multiple space robots to execute exploration tasks. To reduce the completion latency of exploration tasks, we model the joint problem of path planning and task assignment. then we propose a combination algorithm named Branch addition path planning and Task Assignment (BTA). Finally, we implement a series of experiments to evaluate the performance of the proposed algorithms. Experimental results show that the proposed algorithm performs better than the Random path planning and Task Assignment algorithm (RTA) constructed also in this paper. Specifically, BTA performs better than RTA in terms of completion latency and BTA can save more fuel than RTA. Furthermore, the path planning algorithms forward search branch addition of BTA performs more stably than the random path planning of RTA in terms of running time.

关键词： Service robots programming Path planning Space exploration parallel architectures Fuels Task analysis

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A parallel Algorithm to Construct Node-Independent Spanning Trees on the Line Graph of Locally Twisted Cube

A Parallel Algorithm to Construct Node-Independent Spanning ...

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international symposium on parallel architectures, algorithms and programming (paap)

作者： Zhiyong Pan Baolei Cheng Jianxi Fan Huanwen Zhang School of Computer Science and Technology Soochow University Suzhou China

ISBN: (纸本)9781665496407

An interconnection network can be abstracted into a graph, and the basic mathematical research in the graph can provide a good reference for the research in the practical application. the study of node-independent spanning trees (node-ISTs) in a graph has received extensive attention because of their application in reliable communication, fault-tolerant broadcasting and secure message distribution, and has achieved remarkable results on many special networks. But there are few results in the line graph of them. As one of the typical variations of hypercube, locally twisted cube has many excellent properties, whose line graph has all the advantages of locally twisted cube. So it makes sense to do some research on the line graph of locally twisted cube. In this paper, we propose a parallel algorithm to construct $2n-2$ node-ISTs rooted at node $[u,\ N(u, 2)]$ , where $u$ is an arbitrary node on locally twisted cube and $n\geq 1$ . And the correctness of our algorithm is proved.

关键词： Fault tolerance Fault tolerant systems programming NIST Broadcasting Hypercubes parallel architectures

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Efficient Distributed parallel Aligning Reads and Reference Genome with Many Repetitive Subsequences Using Compact de Bruijn Graph

Efficient Distributed Parallel Aligning Reads and Reference ...

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international symposium on parallel architectures, algorithms and programming (paap)

作者： Yao Li Cheng Zhong Danyang Chen Jinxiong Zhang Mengxiao Yin Key Laboratory of Parallel School of Computer Electronics and Information Distributed Computing Technology in Guangxi Universities Guangxi University Nanning China

ISBN: (纸本)9781665496407

A large number of reads generated by the next generation sequencing platform will contain many repetitive subsequences. Effective localizing and identifying genomic regions containing repetitive subsequences will contribute to the subsequent genomic data analysis. To accelerate the alignment between large-scale short reads and reference genome with many repetitive subsequences, this paper develops a compact de Bruijn graph based short-read alignment algorithm on distributed parallel computing platform. the algorithm uses resilient distributed data sets (RDDS) to perform calculations in memory, and executes the broadcast method to distribute short reads and reference genome to the computing nodes to reduce the data communication time on the cluster system, and the number of RDD partitions is set to optimize the performance of parallel aligning algorithm. Experimental results on real datasets show that compared with the compact de Bruijn graph based sequential short-read alignment algorithm, our implemented distributed parallel alignment algorithm achieves good acceleration on the premise of obtaining the same correct alignment percentage as a whole, and compared with existing distributed parallel alignment algorithms, the implemented parallel algorithm can more quickly complete the alignment between large-scale short reads and reference genome with highly repetitive subsequences.

关键词： Sequential analysis Genomics Clustering algorithms Distributed databases programming Partitioning algorithms parallel architectures

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CUDA Grid-Level Task Progression algorithms 17

CUDA Grid-Level Task Progression Algorithms

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2015 IEEE 17th international Conference on High Performance Computing and Communications (HPCC)

作者： Kartsaklis, Christos Joubert, Wayne Hernandez, Oscar R. Eisenbach, Markus Elwasif, Wael R. Bernholdt, David E. Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (纸本)9781479989379

Tasking is a prominent parallel programming model. In this paper we conduct a first study into the feasibility of task-parallel execution at the CUDA grid, rather than the stream/kernel level, for regular, fixed in-out dependency task graphs, similar to those found in wavefront computational patterns, making the findings broadly applicable. We propose and evaluate three CUDA task progression algorithms, where threadblocks cooperatively process the task graph, and argue about their performance in terms of tasking throughput, atomics and memory IO overheads. Our initial results demonstrate a throughput of 38 million tasks/second on a Kepler K20X architecture.

关键词： parallel architectures parallel programming CUDA grid-level task progression algorithm CUDA task progression algorithm Kepler K20X architecture parallel programming model wavefront computational pattern Computational modeling Graphics processing units Instruction sets Kernel parallel processing Radiation detectors Runtime

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Mapping YOLOv4-Tiny on FPGA-Based DNN Accelerator by Using Dynamic Fixed-Point Method

Mapping YOLOv4-Tiny on FPGA-Based DNN Accelerator by Using D...

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international symposium on parallel architectures, algorithms and programming (paap)

作者： Peng Li Cheng Che State Key Laboratory of Information Security Institute of Information Engineering Chinese Academy of Sciences Beijing China School of Cyber Security University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665496407

In the past few decades, with the large-scale application of deep learning technology, the neural network inference speed problem is becoming more and more severe, especially in some mobile and embedded real-time processing systems. To improve the inference speed, some software optimization techniques have been proposed by previous researchers. However, these methods only focused on the model self and still cannot meet the rapid development of large and complex deep learning models. Fortunately, deep neural network (DNN) accelerators based on FPGA SoC has opened a promising opportunity for the real-time inference. In this paper, we proposed a novel 16-bit dynamic fixed-point number quantization method to map the object detection network YOLOv4-tiny into FPGA-based heterogeneous deep learning accelerators. We evaluate this model in Xilinx Zynq-7020 SoC on the ZedBoard platform. Experiment on coco dataset shows that this approach can improve the model inference speed to 4× than pure CPU platform, and the accuracy loss is negligible with only 3-5%. this mapping method can be competitive with or even superior to other state-of-the-art accelerating method in deep learning fields.

关键词： Deep learning Quantization (signal) Neural networks programming Real-time systems Software parallel architectures

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Reducing TLB Miss Penalty on GPUs via Unified Multi-level PWB and PWC

Reducing TLB Miss Penalty on GPUs via Unified Multi-level PW...

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international symposium on parallel architectures, algorithms and programming (paap)

作者： Yang Lin Dunbo Zhang Chaoyang Jia Qiong Wang Li Shen School of Computer NUDT Changsha China

ISBN: (纸本)9781665496407

Recently, GPUs are found to be used across a broad range of domains. To support virtual memory, which is required by most applications at present, the address translation process is introduced to GPU side. However, many applications demonstrate that an irregular memory access pattern, in which accesses are poor structured and often data dependent, makes performance worse especially with virtual-to-physical address translations. Modern memory management unit (MMU) employs caching, e.g. page walk buffer (PWB) and page walk cache (PWC), and scheduling mechanisms to accelerate address translations after TLB misses. Constrained by the linear table structure of traditional PWB and PWC, they hold lots of redundant information, which further limits the performance of irregular applications. Although nonlinear structure can eliminate the redundancy, it requires sequential look-up on PWB and PWC, which brings greater performance loss. In this paper, we propose a unified multi-level PWB and PWC structure that can eliminate the redundancy while enabling parallel look-up. We also design four corresponding address translation processes to ensure the efficiency of the new structure. We evaluate our design with real-world benchmarks under GPGPU-Sim simulator. Results show that our design achieves 42.6% IPC improvement.

关键词： Memory management Graphics processing units Termination of employment programming Benchmark testing parallel architectures

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A Heuristic SAT Problems Solving Method based on LSTM Network

A Heuristic SAT Problems Solving Method based on LSTM Networ...

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international symposium on parallel architectures, algorithms and programming (paap)

作者： Yichuan Wang Xiaolong Liang Xinhong Hei Lei Zhu Wenjiang Ji College of Computer Science and Engineering Xi'an University of Technology Xi'an China

ISBN: (纸本)9781665496407

Boolean Satisfiability Problem(SAT) is a well known determination Problem. *** proved in 1971 that SAT Problem is the first NP-Complete (NPC) Problem in the world, namely, any non-deterministic Polynomial (NP) Problem can be specified with the SAT Problem for solving in Polynomial time. therefore, Boolean satisfiability problem (SAT) can be extended to many practical applications, such as integrated circuit design optimization, biological genes, artificial intelligence, Internet, etc. And there are a lot of NP problems in cryptography. therefore, the study of SAT Problem is of great significance to cryptography. In this paper, we design a heuristic SAT solving algorithm based on LSTM (Long Short-Term Memory) recurrent neural networks. First of all, based on LSTM, we train the model as an end-to-end SAT Solver, which can output 0 or 1 to represent the satisfiability of each SAT problem. then we extract the high-dimensional output of the LSTM network and carry out k-means clustering analysis. Finally, we assign the obtained results as the initial value of the variables of the SAT problem, and inspire two types of classical algorithms (complete algorithm and incomplete algorithm) to solve the SAT problem respectively, so as to accelerate the solving process. In the experiment, we demonstrated the test results of SAT problems with different sizes, and the results show that the LSTM-WalkSAT and LSTM-DPLL based heuristic SAT solving methods can significantly improve the solving efficiency of the original complete or incomplete SAT solving algorithms.

关键词： Integrated circuit synthesis Recurrent neural networks Heuristic algorithms Clustering algorithms programming parallel architectures Internet

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