this paper describes the design and capabilities of a simulation program that modelsthe behavior of a token-ring access local area network (LAN). Such networks consist of a variety of devices connected to a high spee...
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A description is given of the design and capabilities of a simulation program that modelsthe behavior of a token-ring access local area network (LAN). Such networks consist of a variety of devices connected to a high...
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ISBN:
(纸本)0818607661
A description is given of the design and capabilities of a simulation program that modelsthe behavior of a token-ring access local area network (LAN). Such networks consist of a variety of devices connected to a high-speed transmission medium having a geographic extent limited to a few kilometers. Topologically, the transmission medium and devices constitute a closed loop or ring. Devices transmit messages on the ring only after obtaining control of a permission token that regulates access to the transmission medium. Attention is focused on the token-ring access protocol since the available evidence suggests that this protocol results in small delays at light workloads and controlled delay at heavy workloads.
A Lisp machine architecture that supports efficient list manipulation is presented. this Lisp architecture is organized as two processing units: a list processor (LP) that performs all-list related operations and mana...
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ISBN:
(纸本)081860719X
A Lisp machine architecture that supports efficient list manipulation is presented. this Lisp architecture is organized as two processing units: a list processor (LP) that performs all-list related operations and manages the list memory, and an evaluation processor (EP) that maintains the addressing and control environment. the LP contains a translation table (LPT) that maps a small set of list identifiers into the physical memory addresses of objects. Essentially, the LP and LPT virtualize a list. the EP then operates on these virtualized lists. Such an organization permits the overlap of EP function evaluation with LP memory accesses and management, thus reducing the performance penalties typically associated with Lisp list manipulation activities. Trace-driven simulations were used to evaluate this architecture. From the evaluation a relatively small LPT is seen to be sufficient, and to yield 'hit rates' on data accesses higher than those of a data cache of comparable size.
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