SAT-based Bounded Model Checking (BMC), though a robust and scalable verification approach, still is computationally intensive, requiring large memory and time. Interestingly, withthe recent development of improved S...
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this paper presents a method for taking advantage of the efficiency of symbolic model checking using disjunctive partitions, while keeping the number and the size of the partitions small. We define a restricted form o...
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BDDs allow succinct symbolic representation of digital circuits. Symmetry reduction factors out redundancy inherent in the regular organization of many systems. Both are successful techniques for combating state space...
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We propose new, tractably (in some cases provably) efficient algorithmic methods for exact (sound and complete) parameterized reasoning about cache coherence protocols. For reasoning about general snoopy cache protoco...
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the proceedings contain 35 papers. the special focus in this conference is on correcthardwaredesign and verificationmethods. the topics include: hardware synthesis using SAFL and application to processor design;app...
ISBN:
(纸本)3540425411
the proceedings contain 35 papers. the special focus in this conference is on correcthardwaredesign and verificationmethods. the topics include: hardware synthesis using SAFL and application to processor design;applications of hierarchical verification in model checking;pruning techniques for the sat-based bounded model checking problem;heuristics for hierarchical partitioning with application to model checking;efficient reachability analysis and refinement checking of timed automata using BDDS;deriving real-time programs from duration calculus specifications;reproducing synchronization bugs with model checking;register transformations with multiple clock domains;coverability analysis using symbolic model checking;verification of basic block schedules using RTL transformations;parameterized verification of the flash cache coherence protocol by compositional model checking;towards provably-correcthardware compilation tools based on pass separation techniques;a higher-level language for hardware synthesis;hierarchical verification using an MDG-HOL hybrid tool;efficient debugging in a formal verification environment;using combinatorial optimization methods for quantification scheduling;formal verification of the vamp floating point unit;refinement-based formal verification of asynchronous wrappers for independently clocked domains in systems on chip;formal verification of conflict detection algorithms;induction-oriented formal verification in symmetric interconnection network s;a framework for microprocessor correctness statements;from operational semantics to denotational semantics for verilog and efficient verification of a class of linear hybrid automata using linear programming.
the paper investigates specification, verification and test generation for synchronous and asynchronous circuits. the approach is called Dill (Digital Logic in Lotos – the ISO Language Of Temporal Ordering Specificat...
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It is explained howDill (Digital Logic in Lotos) can specify and analyse hardware timing characteristics using ET-Lotos (Enhanced Timed Lotos – the ISO Language Of Temporal Ordering Specification). hardware functiona...
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For the formal specification and verification of real-time systems we use the modular formalism Cottbus Timed Automata (CTA), which is an extension of timed automata [AD94]. Matrix-based algorithms for the reachabilit...
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ISBN:
(纸本)3540425411
For the formal specification and verification of real-time systems we use the modular formalism Cottbus Timed Automata (CTA), which is an extension of timed automata [AD94]. Matrix-based algorithms for the reachability analysis of timed automata are implemented in tools like Kronos, Uppaal, HyTech and Rabbit. A new BDD-based version of Rabbit, which supports also refinement checking, is now available.
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