the proceedings contain 111 papers. the topics discussed include: storage-aware value prediction;computation reduction techniques for vector median filtering and their hardware implementation;a novel VLSI architecture...
ISBN:
(纸本)9780769541716
the proceedings contain 111 papers. the topics discussed include: storage-aware value prediction;computation reduction techniques for vector median filtering and their hardware implementation;a novel VLSI architecture of fixed-complexity sphere decoder;a computation and power reduction technique for H.264 intra prediction;hardware-based speed up of face recognition towards real-time performance;a multicore embedded processor for fingerprint recognition;H.264 color components video decoding parallelization on multi-core processors;a fast analytical approach to multi-cycle soft error rate estimation of sequential circuits;test patterns compression technique based on a dedicated SAT-Based ATPG;gracefully degrading circuit controllers based on polytronics;reconfigurable fault-tolerant system sychronization;a memetic approach for nanoscale hybrid circuit cell mapping;and the use of genetic algorithm to derive correlation between test vector and scan register sequences and reduce power consumption.
the proceeding contains 94 papers. the topics discussed include: the challenges for high performance embedded systems;digital RF;deep sub-100 nm design challenges;new directions in mobile device architectures;robustne...
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ISBN:
(纸本)0769526098
the proceeding contains 94 papers. the topics discussed include: the challenges for high performance embedded systems;digital RF;deep sub-100 nm design challenges;new directions in mobile device architectures;robustness in SOC design;towards performance-oriented pattern-based refinement of synchronous models onto NoC communication;resource-efficient routing and scheduling of time-constrained network-on-chip communication;on cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures;partition based dynamic 2D HW multitasking management;global analysis of resource arbitration for MPSoC;energy-efficient cache coherence for embedded multi-processor systems through application-driven snoop filtering;comparison of GALS and synchronous architectures with MPEG-4 video encoder on multiprocessor system-on-chip FPGA;and multi-bank main memory architecture with dynamic voltage frequency scaling for system energy optimization.
the proceedings contain 109 papers. the topics discussed include: Human++: key challenges and trade-offs in embedded systemdesign for personal health care;cryptographic contests: toward fair and comprehensive benchma...
ISBN:
(纸本)9780769544946
the proceedings contain 109 papers. the topics discussed include: Human++: key challenges and trade-offs in embedded systemdesign for personal health care;cryptographic contests: toward fair and comprehensive benchmarking of cryptographic algorithms in hardware;generalized if-then-else operator for compact polynomial representation of multi output functions;on the cascade implementation of multiple-output sparse logic functions;on failure rate assessment using an executable model of the system;a cost effective centralized adaptive routing for networks-on-chip;numeral-based crosstalk avoidance coding to reliable NoC design;optimal selection of function implementation in a hierarchical configware synthesis method for a coarse grain reconfigurable architecture;hardware reuse in modern application-specific processors and accelerators;and SEU simulation framework for Xilinx FPGA: first step towards testing fault tolerant systems.
the proceedings contain 99 papers. the topics discussed include: secure, real-time and multi-threaded general-purpose embedded Java microarchitecture;decoupling of computation and communication with a communication as...
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ISBN:
(纸本)076952978X
the proceedings contain 99 papers. the topics discussed include: secure, real-time and multi-threaded general-purpose embedded Java microarchitecture;decoupling of computation and communication with a communication assist;an implementation of an address generator using hash memories;a hardware/software co-design vs. hardware implementation of the modular exponentiation using the sliding-window method with constant-length partitioning;alternatives in designing level-restoring buffers for interconnection networks in Field-Programmable Gate Arrays;execution-time prediction for dynamic streaming applications with task-level parallelism;controller design and verification for a pipeline image processor based on an extended Petri net;design method for numerical function generators based on polynomial approximation for FPGA implementation;and graph matching constraints for synthesis with complex components.
the proceedings contain 115 papers. the topics discussed include: composable resource sharing based on latency-rate servers;storage architecture for an on-chip multi-core processor;double-precision Gauss-Jordan algori...
ISBN:
(纸本)9780769537825
the proceedings contain 115 papers. the topics discussed include: composable resource sharing based on latency-rate servers;storage architecture for an on-chip multi-core processor;double-precision Gauss-Jordan algorithm with partial pivoting on FPGAs;distributed collaborative design of a mixed-signal IP component;a hazard-free delay-insensitive 4-phase on-chip link using MVCM signaling;a priority-based budget scheduler with conservative dataflow model;improving the performance of the divide-add fused operation using variable latency quotient;an effective replacement strategy of cache memory for an SMT processor;an evaluation of behaviors of S-NUCA CMPs running scientific workload;a dynamic hybrid cache coherency protocol for shared-memory MPSoC;streaming reduction circuit;variable latency rounding for Goldschmidt algorithm with parallel remainder estimation;and pulse generation for on-chip data transmission.
the proceedings contain 76 papers. the topics discussed include: multi-media applications and imprecise computation;wireless sensor systems - Constraints and opportunities;BIST technique for GALS systems;functional ve...
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ISBN:
(纸本)0769524338
the proceedings contain 76 papers. the topics discussed include: multi-media applications and imprecise computation;wireless sensor systems - Constraints and opportunities;BIST technique for GALS systems;functional vectors generation for RT-Level verilog descriptions based on path enumeration and constraint logic programming;power-composition profile driven Co-synthesis with power management selection for dynamic and leakage energy reduction;a low-power FIR filter using combined residue and radix-2 signed-digit representation;approximating trigonometric functions withthe laws of sines and cosines using the logarithmic number system;characterization of wavelet-based image coding systems for algorithmic fault detection;improved fault emulation for synchronous sequential circuits;and defect-oriented test- and layout-generation for standard-cell ASIC designs.
the proceedings contain 108 papers. the topics discussed include: large scale on-chip networks: an accurate multi-FPGA emulation platform;LIME: a low-latency and low complexity on-chip mesochronous link with integrate...
ISBN:
(纸本)9780769532776
the proceedings contain 108 papers. the topics discussed include: large scale on-chip networks: an accurate multi-FPGA emulation platform;LIME: a low-latency and low complexity on-chip mesochronous link with integrated flow control;synthesis of flexible fault-tolerant schedules with preemption for mixed soft and hard real-time systems;embedded multicore implementation of a H.264 decoder with power management considerations;a network-on-chip channel allocator for run-time task scheduling in multi-processor system-on-chips;analyzing scalability of deblocking filter of H.264 via TLP exploitation in a new many-core architecture;concurrent error detection for a network of combinational logic blocks implemented with memory embedded in FPGAs;analysis of power management strategies for a large-scale SoC platform in 65nm technology;utilization of all levels of parallelism in a processor array with subword parallelism;code generation from statecharts: simulation of wireless sensor networks;and VLSI implementation of a cryptography-oriented reconfigurable array.
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