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Energy-Efficient Static Priority and Speed Assignment for real-time Tasks with Non-Deterministic Release times

Energy-Efficient Static Priority and Speed Assignment for Re...

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16th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Perathoner, Simon thiele, Lothar Chen, Jian-Jia Swiss Fed Inst Technol Comp Engn & Networks Lab TIK Zurich Switzerland KIT Inst Proc Control & Robot IPR Karlsruhe Germany

ISBN: (纸本)9780769541556

Dynamic Voltage Scaling (DVS) has been widely used for decreasing the dynamic power dissipation of processors. For real-time systems, DVS techniques have been developed that permit to meet the timing constraints of multiple real-time tasks and at the same time reduce the overall dynamic energy consumption. Known methods for static priority DVS scheduling are, however, either restricted to simple periodic/sporadic task release patterns or presume full a priori knowledge of task release times. Moreover, none of the present approaches considers the optimization of task priorities for reducing the energy consumption. In this paper we explore how to determine the static priorities and individual execution speeds (supply voltages) of multiple tasks with non-deterministic release times bounded by arrival curves such that the energy consumption is reduced and the real-time constraints are met. the result are different heuristics for the design of DVS-based real-time systems with static priorities. We show that the proposed methodology leads to energy-efficient system designs and demonstrate the applicability of the approach by means of experiments.

关键词： energy consumption time constraints task priorities Daphne virus S Energy efficiency Religious Missions Power dissipation real-time systems VOLTAGE

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VM-Based real-time Services for Automotive Control applications

VM-Based Real-Time Services for Automotive Control Applicati...

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16th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Masrur, Alejandro Droessler, Sebastian Pfeuffer, thomas Chakraborty, Samarjit Tech Univ Munich Inst Real Time Comp Syst Munich Germany ReliaTec GmbH Garching Germany

ISBN: (纸本)9780769541556

Techniques for hardware virtualization have been successfully used to provide hardware-independent services and increase isolation between applications in the desktop domain. However, these characteristics make hardware virtualization also interesting for other domains like those involving control tasks. Since these techniques were initially not conceived for this kind of environments where, in particular, timing constraints must be guaranteed, it is necessary to analyze their behavior and investigate the viability of possible solutions based on them. In this paper, we are concerned with using VMs (Virtual Machines) to provide real-time services in the context of automotive control applications. For this purpose, we make use of the Xen hypervisor to design a real-time control loop on the top of a virtualization layer. We first analyze a typical Xen configuration and identify problems that arise when it is used for real-time applications. We show that the worst-case performance of Xen's standard SEDF scheduler (Simple Earliest Deadline First) can be improved by incorporating some minimal modifications. In addition, in order to reduce latency and jitter in a real-time control loop, we propose a new scheduler for the Xen hypervisor that uses the concept of a real-time VM. real-time VMs are then scheduled before any other VM and under a fixed-priority policy. the proposed VM-based solution is shown to guarantee timing constraints typically encountered in automotive control applications. We further illustrate this through an extensive set of experiments.

关键词： Virtualization real time control automotive engineering virtual machines sun shields control task time constraints Legal Services PROCESS CONTROL applications speed control application real-time application program Voltmeter Jitter scheduler program

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A Study of Utilization Bound and Run-time Overhead for Cluster Scheduling in Multiprocessor real-time systems

A Study of Utilization Bound and Run-Time Overhead for Clust...

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16th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Qi, Xuan Zhu, Dakai Aydin, Hakan Univ Texas San Antonio Dept Comp Sci San Antonio TX 78249 USA George Mason Univ Dept Comp Sci Fairfax VA 22030 USA

ISBN: (纸本)9780769541556

Cluster scheduling, where processors are grouped into clusters and the tasks that are allocated to one cluster are scheduled by a global scheduler, has attracted attention in multiprocessor real-time systems research recently. In this paper, by adopting optimal global schedulers within each cluster, first we investigate the worstcase utilization bound for cluster scheduling. Specifically, for a system with m homogeneous clusters where each cluster has k processors, we show that the worstcase achievable system utilization is left perpendicular k/alpha right perpendicular . m+1/left perpendicular k/alpha right perpendicular + 1 . k, where a is the maximum utilization for the periodic tasks considered. By focusing on an efficient optimal global scheduler, namely the boundary-fair (Bfair) algorithm, we propose a period-aware partitioning heuristic aiming at reducing the scheduling overhead. Simulation results show that the percentage of task sets that can be scheduled is significantly improved under cluster scheduling even for small-size clusters (e.g., k = 2). Moreover, the proposed period-aware partitioning heuristic markedly reduces the scheduling overhead of cluster scheduling with Bfair.

关键词： boundary fair algorithm cluster scheduling multiprocessing systems multiprocessor real time systems optimal global scheduler period aware partitioning heuristic processor scheduling real-time systems run time overhead utilization bound

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Flexible resource management for Self-X systems: An evaluation

Flexible resource management for Self-X systems: An evaluati...

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2010 13th ieee international Symposium on Object/Component/Service-Oriented real-time Distributed computing Workshops, ISORC Workshops 2010

作者： Oberthür, Simon Zaremba, Leszek Lichte, Hermann Simon Department of Design of Distributed Embedded Systems Heinz Nixdorf Institute University of Paderborn Paderborn Germany Computer Networks Group University of Paderborn Paderborn Germany

ISBN: (纸本)9780769540382

In classical real-time systems the resources for an application are allocated at system start so that every resource request can be fulfilled in future. this would lead to much internal waste of resources in the case of modern Self-X systems, because these systems have highly dynamic resource consumptions. the Flexible Resource Manager (FRM) was developed to overcome this problem. the manager puts temporarily unused resources at other applications' disposal. In this paper the FRM approach is evaluated by concrete application examples and randomly generated applications. © 2010 ieee.

关键词： real time systems

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Designing and Implementing a Portable, Efficient Inter-Core Communication Scheme for embedded Multicore Platforms

Designing and Implementing a Portable, Efficient Inter-Core ...

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16th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Hung, Shih-Hao Yang, Wen-Long Tu, Chia-Heng Natl Taiwan Univ Grad Inst Networking & Multimedia Taipei 106 Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei 106 Taiwan

ISBN: (纸本)9780769541556

In the recent years, multicore processor designs have become increasingly popular for embedded applications, but diversified inter-core communication mechanisms have led to the difficulties in software development, integration and migration. A unified, portable, and efficient inter-core communication mechanism would have helped reduce these difficulties significantly, but such a solution did not exist today. We proposed a scheme called MSG, which provides users with a set of essential message-passing programming interfaces adopted from MPI and MCAPI, including blocking and non-blocking point-to-point communications, one-sided communications, and collective operations. We experimented and evaluated our design methodology with the case study on the IBM CELL, a popular heterogeneous multicore platform. On the CELL platform, our MSG library fitted in the 256KB local memory on each individual processor core and outperformed two existing communication libraries, DaCS and CIVIL. With a systematic approach, we showed how optimization could be done on the CELL platform to improve the performance of the MSG library. Hopefully, our experiences help the design and development of communication libraries for existing and future multicore platforms and embedded applications.

关键词： multicore programming inter-core communication message-passing embedded systems MPI MCAPI

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Combining Prefetch with Instruction Cache Locking in Multitasking real-time systems

Combining Prefetch with Instruction Cache Locking in Multita...

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16th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Aparicio, Luis C. Segarra, Juan Rodriguez, Clemente Vinals, Victor Univ Zaragoza Dpt Informat & Ingn Sistemas Zaragoza Spain Univ Zaragoza Inst Invest Ingn Arag I3A Network Excellence High Performance & Embedded Ar Zaragoza Spain Univ Basque Country Dpt Arquitectura & Tecnol Comp Leioa Spain

ISBN: (纸本)9780769541556

In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. this is complex with variable latency hardware usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. Lock-MS is an ILP based method to obtain the best selection of memory lines to be locked in a dynamic locking instruction cache. In this paper we first propose a simple memory architecture implementing the next-line tagged prefetch, specially designed for hard real-time systems. then, we extend Lock-MS to add support for hardware instruction prefetch. Our results show that the WCET of a system with prefetch and an instruction cache with size 5% of the total code size is better than that of a system having no prefetch and cache size 80% of the code. We also evaluate the effects of the prefetch penalty on the resulting WCET, showing that a system without prefetch penalties has a worst-case performance 95% of the ideal case. this highlights the importance of a good prefetch design. Finally, the computation time of our analysis method is relatively short, analyzing tasks of 96 KB with 10(65) paths in less than 3 minutes.

关键词： WCET prefetch instruction cache

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ISORC 2010 - 2010 13th ieee international Symposium on Object/Component/Service-Oriented real-time Distributed computing

ISORC 2010 - 2010 13th IEEE International Symposium on Objec...

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13th ieee international Symposium on Object, Component, and Service-Oriented real-time Distributed computing, ISORC 2010

ISBN: (纸本)9780769540375

the proceedings contain 64 papers. the topics discussed include: dynamic policy-driven quality of service in service-oriented systems;a scheme for reliable real-time messaging with bounded delays;energy-saving mechanisms in the time-triggered architecture;model-based programming of modular robots;design and performance evaluation of binary code packing for protecting embedded software against reverse engineering;architectural and behavioral modeling with AADL for fault tolerant embedded systems;model-driven development of a web service-oriented architecture and security policies;real-time-component based software architecture for QoS-adaptive networked multimedia applications;flexible resource management for self-x systems: an evaluation;real-time distribution of time-dependant tasks in heterogeneous environments;towards a framework for self-adaptive reliable network services in highly-uncertain environments;and policy-based reprogramming for wireless sensor networks.

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Context-based Analysis of System Execution Traces for Validating Distributed real-time and embedded System Quality-of-Service Properties

Context-based Analysis of System Execution Traces for Valida...

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16th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Hill, James H. Indiana Univ Purdue Univ Dept Comp & Informat Sci Indianapolis IN 46202 USA

ISBN: (纸本)9780769541556

System execution traces are useful artifacts for capturing distributed system behavior and validating quality-of-service (QoS) properties, such as end-to-end response time, throughput, and scalability. Although system execution traces assist in validating QoS properties, system execution traces are very dense. this is because system execution traces capture a system's complete behavior and execution in its target environment, which can consist of many components deployed across many hosts that execute for long periods of time. It therefore can be hard for distributed system testers to effectively analyze different views of QoS properties using system execution traces and/or pinpoint performance bottlenecks that need to be resolved. this paper provides two contributions on validating distributed system QoS properties. First, this paper presents Aspects for System Execution Traces (AsSET), which is a join point model for applying aspects to system execution traces and enabling context-based analysis of system execution traces. Secondly, it shows how applying AsSET to a representative enterprise distributed system can improve QoS analytical capabilities for distributed system testers. the tools and techniques discussed in this paper have been realized in an open-source system execution modeling tool named CUTS, which is currently used on several industry-related projects.

关键词： context-based analysis aspects join point model QoS validation system execution traces

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Detecting, Locating, and Tracking Hacker Activities within a WLAN Network

Detecting, Locating, and Tracking Hacker Activities within a...

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16th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Shum, Kevin C. Ng, Joseph K. Hong Kong Baptist Univ Dept Comp Sci Kowloon Tong Hong Kong Peoples R China

ISBN: (纸本)9780769541556

With a good location estimation integrated into a Wi-Fi surveillance system, system administrator can closely monitor the network traffic as well as the behavior of the mobile users. Hence, there is a growing demand to have a quick and efficient way to indentify a specific group of people, or devices or asset within a controlled wireless network. In our proposed system, all the Wi-Fi traffic and information especially the MAC addresses and RSSI from the mobile clients (i.e. Wi-Fi devices) can be sniffed by an open-source Wi-Fi access point (AP) with custom-made embedded software program and without pre-loading any client program on the mobile user devices. these sniffed information is then analyzed and stored in a database which will help network administrator to monitor the wireless network for surveillance purpose and security concerns. In summary, this paper proposes a wireless LAN system that can detect, locate and track down wireless communication within the system by modifying the embedded software in off-the-shelf WLAN APs. Experiment results have shown that abnormal wireless activities can be detected and by our signal strength based localization algorithm, positions of these wireless mobile devices can be identified and be tracked within meters inside our WLAN system.

关键词： Location Estimation Signal Strength Based Localization Ubiquitous computing Wi-Fi Positioning position estimation Ubiquitous computing wireless local area network (WLAN) Wi-Fi Wireless networks embedded software traffic network network administrator Computer Hackers Mobile devices Received Signal Strength Indicator

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Design and Implementation for Multi-Level Cell Flash Memory Storage systems

Design and Implementation for Multi-Level Cell Flash Memory ...

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16th ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Hsieh, Jen-Wei Wu, Chung-Hsien Chiu, Ge-Ming Natl Taiwan Univ Sci & Technol Taipei Taiwan InCOMM Technol Co LTD Taipei Taiwan

ISBN: (纸本)9780769541556

NAND flash memory has gained its popularity in a variety of applications as a storage medium due to its low power consumption, non-volatility, high performance, physical stability, and portability. In particular, Multi-Level Cell (MLC) flash memory, which provides a lower cost and higher density solution, has occupied the largest part of NAND flash-memory market share. However, MLC flash memory also introduces new challenges: (1) Pages in a block must be written sequentially. (2) Information to indicate a page being obsoleted cannot be recorded in its spare area. this paper designs an MLC Flash Translation Layer (MFTL) for flash-memory storage systems which takes new constraints of MLC flash memory and access behaviors of file system into consideration. A series of trace-driven simulations is conducted to evaluate the performance of the proposed scheme. Our experiment results show that the proposed MFTL outperforms other related works in terms of the number of extra page writes, the number of total block erasures, and the memory requirement for the management.

关键词： FAT file system flash-memory storage systems multi-level cell flash memory flash memories Cache Memory System microprocessor logic circuit MLC1 gene Storage Medium memory requirements File systems Portability Popularity

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