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检索条件"任意字段=13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications"

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Early Modeling of Linux-Based RTOS Platforms in a SystemC time-Approximate Co-simulation Environment

Early Modeling of Linux-Based RTOS Platforms in a SystemC Ti...

引用

international Symposium on Object-Oriented real-time Distributed computing

作者： Hector Posadas Eugenio Villar Dominique Ragot Marcos Martinez Microelectronic Engineering GroupTEISA University of Cantabria Santander Spain Thales Communications Paris France DS2 Design of System on Silicon (DS2) Valencia Spain

the increase of computational power in embedded systems has allowed integrating together hard real-time tasks and rich applications. Complex SW infrastructures containing both RTOS and GPOS are required to handle this complexity. To optimally map system functionality to the hard-RT SW domain, to the general purpose SW domain or to HW peripherals, early performance evaluations at the first steps of the design process are required. Approximate timed co-simulation has been proposed as a fast solution for system modeling at early design steps. this co-simulation technique allows simulating systems at speed close to functional execution, while considering timing effects. As a consequence, system performance estimations can be obtained early, allowing efficient design space exploration and system refinement. To achieve fast simulation speed, the SW code is pre-annotated with time information. the annotated code is then natively executed, performing what is called native-based co-simulation. Previous native-based simulation environments are not prepared to model multi-OS systems, so the performance evaluation of the different SW domains is not possible. this paper proposes a new embedded system modeling solution considering dual RTOS/GPOS systems. A real Linux-based infrastructure has been modeled an integrated into a state-of-the-art co-simulation environment. the resulting solution is capable of modeling and evaluating all HW and SW system components providing the designer with valuable information for early system optimization and design space exploration.

关键词： real time systems embedded system Linux Operating systems Distributed computing Process design Timing System performance Space exploration Power system reliability

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A Study of Utilization Bound and Run-time Overhead for Cluster Scheduling in Multiprocessor real-time systems

A Study of Utilization Bound and Run-Time Overhead for Clust...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Xuan Qi Dakai Zhu Hakan Aydin Department of Computer Science University of Texas San Antonio San Antonio TX USA Department of Computer Science George Mason University Fairfax VA USA

Cluster scheduling, where processors are grouped into clusters and the tasks that are allocated to one cluster are scheduled by a global scheduler, has attracted attention in multiprocessor real-time systems research recently. In this paper, by adopting optimal global schedulers within each cluster, first we investigate the worstcase utilization bound for cluster scheduling. Specifically, for a system with m homogeneous clusters where each cluster has k processors, we show that the worstcase achievable system utilization is (⌊k/α⌋·m+1)/(⌊k/α⌋+1) · k, where a is the maximum utilization for the periodic tasks considered. By focusing on an efficient optimal global scheduler, namely the boundary-fair (Bfair) algorithm, we propose a period-aware partitioning heuristic aiming at reducing the scheduling overhead. Simulation results show that the percentage of task sets that can be scheduled is significantly improved under cluster scheduling even for small-size clusters (e.g., k = 2). Moreover, the proposed period-aware partitioning heuristic markedly reduces the scheduling overhead of cluster scheduling with Bfair.

关键词： Program processors Scheduling Schedules Scheduling algorithm real time systems Context

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VM-Based real-time Services for Automotive Control applications

VM-Based Real-Time Services for Automotive Control Applicati...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Alejandro Masrur Sebastian Drossler thomas Pfeuffer Samarjit Chakraborty Institute of Real-Time Computer Systems Technical University Munich Germany ReliaTec GmbH Garching Germany

Techniques for hardware virtualization have been successfully used to provide hardware-independent services and increase isolation between applications in the desktop domain. However, these characteristics make hardware virtualization also interesting for other domains like those involving control tasks. Since these techniques were initially not conceived for this kind of environments where, in particular, timing constraints must be guaranteed, it is necessary to analyze their behavior and investigate the viability of possible solutions based on them. In this paper, we are concerned with using VMs (Virtual Machines) to provide real-time services in the context of automotive control applications. For this purpose, we make use of the Xen hyper visor to design a real-time control loop on the top of a virtualization layer. We first analyze a typical Xen configuration and identify problems that arise when it is used for real-time applications. We show that the worst-case performance of Xen's standard SEDF scheduler (Simple Earliest Deadline First) can be improved by incorporating some minimal modifications. In addition, in order to reduce latency and jitter in a real-time control loop, we propose a new scheduler for the Xen hyper visor that uses the concept of a real-time VM. real-time VMs are then scheduled before any other VM and under a fixed-priority policy. the proposed VM-based solution is shown to guarantee timing constraints typically encountered in automotive control applications. We further illustrate this through an extensive set of experiments.

关键词： real time systems time factors Hardware Virtual machine monitors Driver circuits Sensors Timing

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Energy-Efficient Static Priority and Speed Assignment for real-time Tasks with Non-deterministic Release times

Energy-Efficient Static Priority and Speed Assignment for Re...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Simon Perathoner Lothar thiele Jian-Jia Chen Computer Engineering and Networks Laboratory (TIK) Swiss Federal Institute of Technology Zurich Switzerland Institute of Process Control and Robotics (IPR) Karlsruhe Institute of Technology Karlsruhe Germany

Dynamic Voltage Scaling (DVS) has been widely used for decreasing the dynamic power dissipation of processors. For real-time systems, DVS techniques have been developed that permit to meet the timing constraints of multiple real-time tasks and at the same time reduce the overall dynamic energy consumption. Known methods for static priority DVS scheduling are, however, either restricted to simple periodic/sporadic task release patterns or presume full a priori knowledge of task release times. Moreover, none of the present approaches considers the optimization of task priorities for reducing the energy consumption. In this paper we explore how to determine the static priorities and individual execution speeds (supply voltages) of multiple tasks with non-deterministic release times bounded by arrival curves such that the energy consumption is reduced and the real-time constraints are met. the result are different heuristics for the design of DVS-based real-time systems with static priorities. We show that the proposed methodology leads to energy-efficient system designs and demonstrate the applicability of the approach by means of experiments.

关键词： Voltage control Energy consumption real time systems Processor scheduling Program processors Jitter Algorithm design and analysis

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Energy Efficient Scheduling for real-time embedded systems with QoS Guarantee

Energy Efficient Scheduling for Real-Time Embedded Systems w...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Linwei Niu Department of Math and Computer Science Claflin University Orangeburg SC USA

While the dynamic voltage scaling (DVS) techniques are efficient in reducing the dynamic energy consumption for the processor, varying voltage alone becomes less effective for the overall energy reduction as the static power is growing rapidly. On the other hand, Quality of Service (QoS) is also a primary concern in the development of today's pervasive computing systems. In this paper, we propose a dynamic approach to minimize the overall energy consumption for soft real-time systems while ensuring the QoS-guarantee. the QoS requirements are deterministically quantified with the window-constraints, which require that at least m out of each non-overlapped window of k consecutive jobs of a task meet their deadlines. Necessary and sufficient conditions for checking the feasibility of task sets with arbitrary service times and periods are developed to ensure that the window-constraints can be guaranteed in the worst case. And efficient scheduling techniques based on pattern variation and dynamic slack reclaiming extensions are proposed to combine the task procrastination and dynamic slowdown to minimize the energy consumption. In contrast to the previous leakage-aware slack reclaiming work which never scales the job speed below the critical speed, we will show that it can be more energy efficient to reclaim the slack with speed lower than the critical speed when necessary. through extensive simulations, our experiment results demonstrate that the proposed techniques significantly outperformed the previous research in both overall and idle energy reduction.

关键词： Quality of service real time systems Dynamic scheduling Power demand Energy consumption Nickel Schedules

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Designing and Implementing a Portable, Efficient Inter-core Communication Scheme for embedded Multicore Platforms

Designing and Implementing a Portable, Efficient Inter-core ...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Shih-Hao Hung Wen-Long Yang Chia-Heng Tu National Taiwan University Taipei TW Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan Graduate Institute of Networking and Multimedia National Taiwan University Taipei Taiwan

In the recent years, multicore processor designs have become increasingly popular for embedded applications, but diversified inter-core communication mechanisms have led to the difficulties in software development, integration and migration. A unified, portable, and efficient inter-core communication mechanism would have helped reduce these difficulties significantly, but such a solution did not exist today. We proposed a scheme called MSG, which provides users with a set of essential message-passing programming interfaces adopted from MPI and MCAPI, including blocking and non-blocking point-to-point communications, one-sided communications, and collective operations. We experimented and evaluated our design methodology with the case study on the IBM CELL, a popular heterogeneous multicore platform. On the CELL platform, our MSG library fitted in the 256KB local memory on each individual processor core and outperformed two existing communication libraries, DaCS and CML. With a systematic approach, we showed how optimization could be done on the CELL platform to improve the performance of the MSG library. Hopefully, our experiences help the design and development of communication libraries for existing and future multicore platforms and embedded applications.

关键词： Distributed databases Data communication Computer architecture Receivers real time systems Protocols Synchronization

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An Approximate Timing Analysis Framework for Complex real-time embedded systems

An Approximate Timing Analysis Framework for Complex Real-Ti...

引用

ieee international conference on Computational Science and Engineering, CSE

作者： Yue Lu thomas Nolte Johan Kraft Mälardalen Real-Time Research Centre Mälardalen University Vasteras Sweden

To maintain, analyze and reuse many of today's Complex real-time embedded systems (CRTES) is very difficult and expensive, which, nevertheless, offers high business value in response to great concern in industry. In such context, not only functional behavior but also non-functional properties of systems have to be assured, i.e., Worst-Case Response time (WCRT) of tasks has to be known. However, due to high complexity of such systems and the nature of the problem, the exact WCRT of tasks is impossible to find in practice, but may only be bounded. In addition, the existing relatively well developed theories for modeling and analysis of real-time systems are having problems which limit their application in the context. In this paper, we address this challenge by presenting a framework for approximate timing analysis of CRTES, namely AESIR-CORES, which provides a tight interval of WCRT estimates of tasks by the usage of two novel contributions. Our evaluation using three models inspired by two fictive but representative industrial CRTES indicates that AESIR-CORES can either successfully obtain the actual WCRT values, or have the potential to bound the unknown actual WCRT values from a statistical perspective.

关键词： Analytical models time factors Timing Data models real time systems Upper bound Monte Carlo methods

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Design and Implementation for Multi-level Cell Flash Memory Storage systems

Design and Implementation for Multi-level Cell Flash Memory ...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Jen-Wei Hsieh Chung-Hsien Wu Ge-Ming Chiu National Taiwan University of Science and Technology Taiwan InCOMM Technologies Company Limited Taiwan

NAND flash memory has gained its popularity in a variety of applications as a storage medium due to its low power consumption, non-volatility, high performance, physical stability, and portability. In particular, Multi-Level Cell (MLC) flash memory, which provides a lower cost and higher density solution, has occupied the largest part of NAND flash-memory market share. However, MLC flash memory also introduces new challenges: (1) Pages in a block must be written sequentially. (2) Information to indicate a page being obsoleted cannot be recorded in its spare area. this paper designs an MLC Flash Translation Layer (MFTL) for flash-memory storage systems which takes new constraints of MLC flash memory and access behaviors of file system into consideration. A series of trace-driven simulations is conducted to evaluate the performance of the proposed scheme. Our experiment results show that the proposed MFTL outperforms other related works in terms of the number of extra page writes, the number of total block erasures, and the memory requirement for the management.

关键词： Ash Memory management Random access memory Switches Writing Merging

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Classification and Analysis of Predictable Memory Patterns

Classification and Analysis of Predictable Memory Patterns

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Benny Akesson Williston Hayes Jr. Kees Goossens Eindhovan University of Technology Netherlands

the verification complexity of real-time requirements in embedded systems grows exponentially with the number of applications, as resource sharing prevents independent verification using simulation-based approaches. Formal verification is a promising alternative, although its applicability is limited to systems with predictable hardware and software. SDRAM memories are common examples of essential hardware components with unpredictable timing behavior, typically preventing use of formal approaches. A predictable SDRAM controller has been proposed that provides guarantees on bandwidth and latency by dynamically scheduling memory patterns, which are statically computed sequences of SDRAM commands. However, the proposed patterns become increasingly inefficient as memories become faster, making them unsuitable for DDR3 SDRAM. this paper extends the memory pattern concept in two ways. Firstly, we introduce a burst count parameter that enables patterns to have multiple SDRAM bursts per bank, which is required for DDR3 memories to be used efficiently. Secondly, we present a classification of memory pattern sets into four categories based on the combination of patterns that cause worst-case bandwidth and latency to be provided. Bounds on bandwidth and latency are derived that apply to all pattern types and burst counts, as opposed to the single case covered by earlier work. Experimental results show that these extensions are required to support the most efficient pattern sets for many use-cases. We also demonstrate that the burst count parameter increases efficiency in presence of large requests and enables a wider range of real-time requirements to be satisfied.

关键词： SDRAM Bandwidth Memory management Switches Clocks real time systems Timing

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Optimizing the Processing Performance of a Smart DMA Controller for LTE Terminals

Optimizing the Processing Performance of a Smart DMA Control...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： David Szczesny Sebastian Hessel Shadi Traboulsi Attila Bilgic Institute of Integrated Systems Ruhr Universität Bochum Bochum Germany

In this paper we present an extended and optimized version of a smart Direct Memory Access (sDMA) controller supporting different on-the-fly protocol stack acceleration concepts for Long Term Evolution (LTE) mobile terminals. In addition to the downlink processing, we analyse different on-the-fly hardware acceleration modes for the uplink protocol stack processing in layer 2 (L2). Moreover, the system performance is further improved by adopting parallelization methods. the efficiency of on-the-fly hardware acceleration is proved by comparing the transport block processing times to those achieved with a conventional hardware accelerator. therefore, a cycle approximate virtual prototype of a state-of-the-art mobile phone platform based on an ARM1176 processor is simulated at LTE-Advanced data rates of up to 1 Gbit/s. In uplink direction, we are able to reduce the complexity in the sDMA controller and simultaneously improve the processing performance in the mobile platform. this is realized by intelligent hardware/software partitioning and an optimized descriptor format. Furthermore, a significant optimization (up to 13 %) of the system performance in a mobile device is achieved by adopting parallelized on-the-fly hardware acceleration modes. We show how the sDMA controller clearly outperforms the traditional approach by reaching speedups of up to 35 % and 66 % for the transport block processing times in uplink and downlink directions, respectively.

关键词： Hardware Multiaccess communication Protocols Acceleration Process control Decoding Software

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