We consider a resource synthesis technique for realtimesystems where dynamic voltage scaling is supported, the energy budget is limited, and the performance of the system depends on how resources and energy are used....
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We consider a resource synthesis technique for realtimesystems where dynamic voltage scaling is supported, the energy budget is limited, and the performance of the system depends on how resources and energy are used. We propose a resource synthesis technique that derives boththe supply voltages and the resource allocation of the tasks in the system to maximize system performance. the resulting system satisfies real-time schedulability and energy requirements.
Code optimization of the offset assignment generated in embeddedsystems allows for power and space efficient systems. We propose a new heuristic that uses edge classification to commutatively transformation and optim...
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Code optimization of the offset assignment generated in embeddedsystems allows for power and space efficient systems. We propose a new heuristic that uses edge classification to commutatively transformation and optimize the assignment. We introduce concept of breakable and unbreakable edges, which assists in selecting edges for path cover and edges for commutative transformation.
Multicore platforms, which include several processing cores on a single chip, are being widely touted as a solution to heat and energy problems that are impediments to single-core chip designs. To accommodate both par...
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Multicore platforms, which include several processing cores on a single chip, are being widely touted as a solution to heat and energy problems that are impediments to single-core chip designs. To accommodate both parallelizable and inherently-sequential applications on the same platform, heterogeneous multicore designs with faster and slower cores have been proposed. In this paper, we consider the problem of scheduling soft real-time workloads on such a platform.
Since high-quality image/video systems based on the JPEG/MPEG compression standards often require power-expensive implementations at relatively high bit-rates, they have not been widely used in low-power wireless appl...
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Wireless Sensor Networks (WSN) have been attracting growing interests for developing a new generation Of large-scale embeddedcomputingsystems, with a great potential for a wide range of applications such as surveill...
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ISBN:
(纸本)9781424408269
Wireless Sensor Networks (WSN) have been attracting growing interests for developing a new generation Of large-scale embeddedcomputingsystems, with a great potential for a wide range of applications such as surveillance, environmental monitoring, emergency medical response or building automation. However, the communication paradigms in wireless sensor networks differ from the ones associated to traditional wireless networks, triggering the need for new communication protocols and architectures. the ART-WiSe (Architecture for real-time communications in Wireless Sensor Networks) framework aims at the design of a scalable multiple-tiered WSN architecture for supporting large-scale embeddedcomputingapplications with critical requirements. An overlay Wireless Local Area Network (Tier-2) serves as a backbone for a WSN (Tier 1), relying on existing standard communication protocols and commercial-off-the-shell (COTS) technologies ieee 802.15.4/ZigBee for Tier I and ieee 802. 11 for Tier-2. this paper outlines ongoing work on the design of the architectural requirements and features for a QoS-aware gateway between both networks.
Two architectural paradigms for the development of hierarchical systems arguably stand out for their flexibility and ease of reconfiguration: the server-based architecture and the priority-band architecture. Whilst th...
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Two architectural paradigms for the development of hierarchical systems arguably stand out for their flexibility and ease of reconfiguration: the server-based architecture and the priority-band architecture. Whilst the former has been deeply investigated, the latter, a fresh addition to a mainstream programming language standard, still lacks an accurate study of its timing behaviour. In this paper we relate those two architectural paradigms and devise timing analysis equations for the priority-band systems off the solid roots of the server-based theory.
In this paper we analyze the influence of the urgency in the timed transitions, and as consequence, in the test suite generation. As result, we formalize rules to generate sequences where the messages exchanged may be...
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In this paper we analyze the influence of the urgency in the timed transitions, and as consequence, in the test suite generation. As result, we formalize rules to generate sequences where the messages exchanged may be instantaneous or delayed. In addition, the generated scenarios are able to detect timing faults. For test generation, we use a prototype tool called HJ2IF. It is based on a test purpose algorithm, called hit-or-jump and it is applied for systems specified using Intermediate Format language (IF).
Energy-efficient designs have played import roles for hardware and software implementations for a decade. Withthe advanced technology of VLSI circuit designs, energy-efficiency can be achieved by adopting the dynamic...
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Energy-efficient designs have played import roles for hardware and software implementations for a decade. Withthe advanced technology of VLSI circuit designs, energy-efficiency can be achieved by adopting the dynamic voltage scaling (DVS) technique. In this paper, we survey the studies for energy-efficient scheduling in real-timesystems on DVS platforms to cover boththeoretical and practical issues.
embedded system design is especially demanding in terms of requirements that need to be satisfied, e.g. real-time processing, cost effectiveness, low energy consumption and reliable operation. these requirements have ...
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Flash memories could be a basis for mass storage withreal-time guarantees if a suitable model for access timing could be established. We describe Flanatoo, a suite of benchmarks which extracts relevant timing informa...
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Flash memories could be a basis for mass storage withreal-time guarantees if a suitable model for access timing could be established. We describe Flanatoo, a suite of benchmarks which extracts relevant timing information from removable flash media such as compact flash (CF) and USB flash drives. We identified three major timing influence factors: the access block size, the accessed address and (to a lesser degree) the written bit pattern. Despite numerous timing anomalies we argue that removable flash media behave more predictably than hard disks and are indeed a potential basis for real-time mass storage.
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