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检索条件"任意字段=13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications"

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Utilization bounds for RM scheduling on uniform multiprocessors

Utilization bounds for RM scheduling on uniform multiprocess...

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12th international conference on embedded and real-time computing systems and applications

作者： Darera, Vivek N. Jenkins, Lawrence Indian Inst Sci LSM Lab EE Dept Bangalore 560012 Karnataka India Indian Inst Sci EE Dept Bangalore Karnataka India

ISBN: (纸本)0769526764

Utilization bounds for Earliest Deadline First(EDF) and Rate Monotonic(RM) scheduling are known and well understood for uniprocessor systems. In this paper, we derive limits on similar bounds for the multiprocessor case, when the individual processors need not be identical. Tasks are partitioned among the processors and RM scheduling is assumed to be the policy used in individual processors. A minimum limit on the bounds for a 'greedy' class of algorithms is given and proved, since the actual value of the bound depends on the algorithm that allocates the tasks. We also derive the utilization bound of an algorithm which allocates tasks in decreasing order of utilization factors. Knowledge of such bounds allows us to carry out very fast schedulability tests although we are constrained by the fact that the tests are sufficient but not necessary to ensure schedulability.

关键词： Multiprocessing systems

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Experiments and investigations for the Personal High Performance computing (PHPC) built on top of the 64-bit processing and clustering systems

Experiments and investigations for the Personal High Perform...

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13th Annual ieee international Symposium and Workshop on Engineering of Computer Based systems

作者： Chang, Victor Univ Southampton Sch Elect & Comp Sci Southampton Hants England

ISBN: (纸本)0769525466

the motivation and objective for this paper is to demonstrate "Personal High Performance computing (PHPC)", which requires only a smaller number of computers, resources and space in the secure wireless home networking (WHN) environment. the PHPC is based on a cluster of the 64-bit AMD machines, which can achieve the following: (a) reducing CPU time by 10% - 50% for a single task;(b) minimizing the memory and hard-disk workload by 50%;(c) running 64-bit software applications successfully;(d) receiving up to 60% better performance in multi-tasking performance;(e) executing fast, robust and accurate calculations, visualization and server-side applications on 32-bit and 64-bit Windows and Linux;(f) ensuring a secure working environment (g) storing a massive amount of data (12 TB, or 12,000 GB) for database and server applications;and (h) successfully integrating with other emerging technologies such as LAN/wireless networks and entertainment systems.

关键词： embedded systems

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Generalized rate analysis for media-processing platforms

Generalized rate analysis for media-processing platforms

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12th international conference on embedded and real-time computing systems and applications

作者： Liu, Yanhong Chakraborty, SamalJit Marculescu, Radu Natl Univ Singapore Dept Comp Sci Singapore 117548 Singapore Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

ISBN: (纸本)0769526764

In this paper we address the "rate analysis" problem for media-processing platforms consisting of multiple processor cores connected in a pipelined fashion. More precisely, we aim at determining tight bounds on the rates at which multimedia streams can be fed into such architectures. these bounds depend on architectural constraints (e.g. the available on-chip memory, bus arbitration policies, etc.), as well as the application characteristics (e.g. application partitioning and mapping, workload rates generated by different tasks, etc.). the proposed framework for rate analysis can be used for fast design space exploration to determine how these bounds change with different architectural parameters, mapping of the application, or changing the QoS requirements associated with the input streams.

关键词： Pipeline processing systems

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Application-driven low-power techniques using dynamic voltage scaling

Application-driven low-power techniques using dynamic voltag...

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12th international conference on embedded and real-time computing systems and applications

作者： Kim, Taewhan Seoul Natl Univ Sch Elect Engn & Comp Engn Seoul South Korea

ISBN: (纸本)0769526764

It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-time applications. the effectiveness comes from the fact that the amount of energy consumption is quadractically proportional to the voltage applied to the processor the penalty is the execution delay, which is linearly and inversely proportional to the voltage. According to the granularity of units to which voltage scaling is applied, the DVS problem is divided into two subproblems: inter-task DVS problem, in which the determination of the voltage is carried out on a task-by-task basis and the voltage assigned to the task is unchanged during the whole execution of the task, and intra-task DVS problem, in which the operating voltage of a task is dynamically adjusted according to the execution behavior to reflect the changes of the required number of cycles to finish the task before the deadline. Frequent voltage transitions may cause an adverse effect on energy minimizatuion due to the increase of the overhead of transition time and energy. In this paper, we survey and describe, in a theoretical aspect, state-of-art techniques of dynamic voltage scaling problems, which include: (1) inter-task DVS problem, (2) intra-task DVS problem, (3) integrated inter-task and intra-task DVS-problem, and (4) transition-aware DVS problem.

关键词： real time systems

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Data Freshness and Overload Handling in embedded systems

Data Freshness and Overload Handling in Embedded Systems

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12th international conference on embedded and real-time computing systems and applications

作者： Gustafsson, thomas Hansson, Jorgen Linkoping Univ Dept Comp & Informat Sci S-58183 Linkoping Sweden Carnegie Mellon Univ Inst Software Engn Pittsburgh PA USA

ISBN: (纸本)0769526764

In this paper we consider data freshness and overload handling in embedded systems. the requirements on data management and overload handling are derived from an engine control software. Data items need to be up-to-date, and to achieve this data dependencies must be considered, i.e., updating a data item requires other data items are up-to-date. We also note that a correct result of a calculation can in some cases be calculated using a subset of the inputs. Hence, data dependencies can be divided into required and not required data items, e.g., only a subset of data items affecting the fuel calculation in an engine control needs to be calculated during a transient overload in order to reduce the number of calculations. Required data items must always be up-to-date, whereas not required data items can be stale. We describe an algorithm that dynamically determines which data items need to be updated taking workload, data freshness, and data relationships into consideration. Performance results show that the algorithm suppresses transient overloads better than (m, k) - and skip-over scheduling combined with established algorithms to update data items. the performance results are collected from an implementation of a real-time database on the realtime operating system mu C/OS-H. To investigate whether the system is occasionally overloaded an offline analysis algorithm estimating period times of updates is presented.

关键词： embedded systems

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Operating system support for proeedural abstraction in embedded systems

Operating system support for proeedural abstraction in embed...

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12th ieee international conference on embedded and real-time computing systems and applications, RTCSA 2006

作者： Yim, Keun Soo Yoo, Jeong-Joon Lee, Jae Don Kim, Jihong Computing Lab. Samsung Advanced Institute of Technology Yongin 449-72 Korea Republic of School of Computer Sci. and Engr. Seol National University Seoul 151-742 Korea Republic of

ISBN: (纸本)0769526764

Procedural abstraction reduces code size by replacing repeated code fragments with call instructions to a sub-routine that executes the repeated fragment. However, in order to build a subroutine, extra instructions are necessary to support the procedural call mechanism. In this paper, we present an operating system level technique which improves the space efficiency of a procedural abstraction-based code compaction technique. the call-related extra instructions are not used in the proposed technique because operating system routines implicitly supports the procedure call and return. the proposed technique consists of three execution modes including one applicable to ROM-based systems. the experimental results show the proposed technique reduces the code size significantly while increasing the execution time slightly. © 2006 ieee.

关键词： Computer operating systems

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Developing embedded kernel for System-On-a-Chip platform of heterogeneous multiprocessor architecture

Developing embedded kernel for System-On-a-Chip platform of ...

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12th international conference on embedded and real-time computing systems and applications

作者： Chen, Jing Liu, Jian-Hong Natl Cheng Kung Univ Dept Elect Engn 1 Univ Rd Tainan 70101 Taiwan

ISBN: (纸本)0769526764

It has been common that modern embedded system products are built on platforms with System-On-a-Chip (SOC) in which two or more different processor cores are put into one single chip and form the architecture Of heterogeneous multiprocessor Although providing high performance at low cost, such architecture brings new design challenges as well as increased complexity in developing embedded software especially at the level of kernel or operating system software. this paper presents our experience in developing an embedded microkernel that runs on embedded system of heterogeneous multiprocessor architecture composed of one general purpose processor (GPP) and one special purpose processor (SPP). Aside from following the traditional approach of monolithic operating system, the option of dual kernels based on microkernel architecture with uniform message-passing mechanism was taken to develop a symmetric embedded microkernel which can be compiled to run separately on each of the different processor cores in the system. the design and the approach not only reduce the software complexity in developing a kernel to manage different processors in a system but also enable a symmetric view from processors of different architectures. A prototype kernel was implemented on a reference design of Texas Instrument's TMS320DSC25 which is a heterogeneous multiprocessor SOC with a GPP of ARM7TDMI core and an SPP of C5409 DSP core.

关键词： embedded systems

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Maximizing guaranteed QoS in (m, k)-firm real-time systems

Maximizing guaranteed QoS in (m, k)-firm real-time systems

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12th ieee international conference on embedded and real-time computing systems and applications, RTCSA 2006

作者： Lin, Jian Cheng, Albert M. K. Real-Time Systems Laboratory Department of Computer Science University of Houston TX 77204 United States

ISBN: (纸本)0769526764

(m,k)-firm constraints have been used to schedule tasks in soft/firm real-time systems under overloaded conditions. In general, they are provided by application designers to guarantee the minimum levels of quality of service (QoS). Many problems concentrating in task schedulability under these constraints were investigated in the last ten years. However, little work has been done in combining the optimization of the QoS and task schedulability subject to these (m, k)-flrm constraints. In this paper, we consider the problem of maximizing the guaranteed performance while maintaining a schedulable task set in periodic firm real-time systems. To quantify the performance, we propose a granularityrelated metric called Granularity of Quality of Service - Reward (GQoS-reward). We then show that maximizing the total GQoS-reward is an NP-Hard problem and a heuristic method to solve the problem is studied. In addition to the improvement to the GQoS, positive effects on other main performance metrics for soft/firm real time systems, such as effective processor utilization (EPU), total accumulated reward and instability, are also supported by the simulation results using our optimization strategy. © 2006 ieee.

关键词： real time systems

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Integrating compiler and system toolkit flow for embedded VLIW DSP processors

Integrating compiler and system toolkit flow for embedded VL...

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12th international conference on embedded and real-time computing systems and applications

作者： Wu, Chi Hsieh, Kun-Yaan Lin, Yung-Chia Wu, Chung-Ju Shih, Wen-Li Chen, S. C. Chen, Chung-Kai Huang, Chien-Ching You, Yi-Ping Lee, Jenq Kuen Natl Tsing Hua Univ Dept Comp Sci Hsinchu 300 Taiwan

ISBN: (纸本)0769526764

To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constraints, distributed register files, variable length encodings for instructions, and special data paths are frequently adopted. this creates challenges to deploy software toolkits for new embedded DSP processors. this article presents our methods and experiences to develop software and toolkit flows for PAC (Parallel Architecture Core) VLIW DSP processors. Our toolkits include compilers, assemblers, debugger, and DSP micro-kernels. We first retarget Open Research Compiler (ORC) and toolkit chains for PAC VLIW DSP processor and address the issues to support distributed register files and ping-pong data paths for embedded VLIW DSP processors. Second, the linker and assmeber are able to support variable length encoding schemes for DSP instructions. In addition, the debugger and DSP micro-kernel were designed to handle dualcore environments. the footprint of micro-kernel is also around I OK to address the code-size issues for embedded devices. We also present the experimental result in the compiler framework by incorporating software pipeline (SWP) policies for distributed register files in PAC architecture. Results indicated that our compiler framework gains performance improvement around 2.5 times against the code generated without our proposed optimizations.

关键词： Digital signal processing

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Proceedings of ASMTA 2006: 13th international conference on Analytical and Stochastic Modelling Techniques and applications

Proceedings of ASMTA 2006: 13th International Conference on ...

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13th international conference on Analytical and Stochastic Modelling Techniques and applications, ASMTA 2006

ISBN: (纸本)9780955301803

the proceedings contain 23 papers. the topics discussed include: analytical interconnection networks model for multi-cluster computing systems;waiting time distribution of the AAL2 multiplexer in UTRAN;approximation of the variance of waiting time in a two-queue time priority system;dimensioning of a deiittering buffer for variable bit rate streams;retrial queuing model for multimedia over downlink in 3.5g wireless networks;a new dynamic priority scheme: performance analysis;analysis of a two-node queuing network with flow control and negative arrivals;potentials and challenges of transient analysis for server and queuing systems;optimization of buffers capacity in tandem queuing systems with batch Markovian arrivals;training hidden non-Markov models;and reliable computation of workload distributions using semi-Markov processes.

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