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Using real-time Logic Synthesis Tool to Achieve Process Control over Wireless Sensor Networks

Using Real-Time Logic Synthesis Tool to Achieve Process Cont...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Jianping Song Aloysius K. Mok Deji Chen M. Nixon Department of Computer Sciences University of Texas Austin Austin TX USA Emerson Process Management Austin TX USA

Wireless sensor networks have been a very active research field in the past few years. However, most of extant research has focused on wireless sensing, such as environmental and habitat monitoring. In this paper, we investigate the feasibility of applying wireless technologies in industrial real-time process control systems. We define a minimum set of assumptions about the underlying sensor networks in order to achieve real-time support for process control. these assumptions are necessary and practical from an industrial perspective. We formulate the modeling of a wireless process control configuration as a multi-processor scheduling problem. the resulting scheduling problem is solved by the scheduler synthesis tool *** to produce a valid configuration for deployment. the deployment, because of the way it is derived, provides real-time wireless support for the controlled processes. Simulation results on data from real plant configurations show that this approach can also drastically reduce potential interferences between wireless transfers

关键词： Logic Network synthesis Process control Wireless sensor networks Job shop scheduling Electrical equipment industry Monitoring Industrial control real time systems Interference

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Balancing Energy vs. Performance in Processors with DiscreteVoltage/Frequency Modes

Balancing Energy vs. Performance in Processors with Discrete...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： M. Marinoni G. Buttazzo University of Pavia Italy Scuola Superiore Sant'' Anna Italy

Applying classical dynamic voltage scaling (DVS) techniques to real-time systems running on processors with discrete voltage/frequency modes causes a waste of computational resources. In fact, whenever the ideal speed level computed by the DVS algorithm is not available in the system, to guarantee the feasibility of the task set, the processor speed must be set to the nearest level greater than the optimal one, thus underutilizing the system. Whenever the task set allows a certain degree of flexibility in specifying timing constraints, rate adaptation techniques can be adopted to balance performance (which is a function of task rates) vs. energy consumption (which is a function of the processor speed). In this paper, we propose a new method that combines discrete DVS management with elastic scheduling to fully exploit the available computational resources. Depending on the application requirements, the algorithm can be set to improve performance or reduce energy consumption, so enhancing the flexibility of the system. A reclaiming mechanism is also used to take advantage of early completions

关键词： Frequency Voltage control Dynamic voltage scaling Energy consumption Timing Processor scheduling real time systems Energy management Algorithm design and analysis Pulse width modulation

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A Software Infrastructure for Wearable Sensor Networks

A Software Infrastructure for Wearable Sensor Networks

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： K. Hanaoka A. Takagi T. Nakajima Department of Computer Science Waseda University Japan

In ubiquitous computing environments, context-awareness is one of the most important research topics. Computers embedded in our surrounding can extract information about a user, and the information makes it possible to offer personalized services according to the user's preference. To extract a large amount of context information, wearable sensor devices become more important in the near future. However, it is not easy to develop context-aware services that use context information from wearable sensor devices because of the gap between low-level sensor information and high-level context that the services require. In this paper, we propose a software infrastructure for wearable sensor networks. We first discuss the requirements to retrieve context information from wearable sensor networks. then, we introduce our software infrastructure named Cinnamon that extracts high-level context from low-level context information retrieved from wearable sensor networks. the software infrastructure makes it dramatically easy to develop context-aware services for wearable sensor networks. We present the design and implementation of Cinnamon, and discuss our current prototype implementation

关键词： Wearable sensors Context-aware services Information retrieval Data mining Prototypes embedded computing Ubiquitous computing Pervasive computing Software prototyping Data analysis

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Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling

Application-Driven Low-Power Techniques Using Dynamic Voltag...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Taewhan Kim School of Electrical Engineering and Computer Science Seoul National University Seoul South Korea

It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-time applications. the effectiveness comes from the fact that the amount of energy consumption is quadractically proportional to the voltage applied to the processor. the penalty is the execution delay, which is linearly and inversely proportional to the voltage. According to the granularity of units to which voltage scaling is applied, the DVS problem is divided into two subproblems: inter-task DVS problem, in which the determination of the voltage is carried out on a task-by-task basis and the voltage assigned to the task is unchanged during the whole execution of the task, and intra-task DVS problem, in which the operating voltage of a task is dynamically adjusted according to the execution behavior to reflect the changes of the required number of cycles to finish the task before the deadline. Frequent voltage transitions may cause an adverse effect on energy minimization due to the increase of the overhead of transition time and energy. In this paper, we survey and describe, in a theoretical aspect, state-of-art techniques of dynamic voltage scaling problems, which include: (1) inter-task DVS problem, (2) intra-task DVS problem, (3) integrated inter-task and intra-task DVS problem, and (4) transition-aware DVS problem

关键词： Dynamic voltage scaling Voltage control Processor scheduling Energy consumption Minimization Circuits Clocks Frequency Timing real time systems

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Algorithm Selectors for Providing Location Estimation Services within a Cellular Radio Network

Algorithm Selectors for Providing Location Estimation Servic...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Junyang Zhou Joseph Kee-Yin Ng Department of Computer Science Hong Kong Baptist University Hong Kong China

Mobile location estimation is becoming an important value-added service for mobile phone operators. Many mobile location estimation algorithms based on the cellular radio networks have been proposed but there exists no general solution since each algorithm has its own advantage depending on specific terrain and environmental factors. In this paper, we propose and investigate three algorithm selectors, one with a LDA classifier and the other two with Bayes classifiers using either a Naive Bayes probabilistic model or a Bayes probabilistic model, to select the best mobile location estimation algorithms from our previous work in order to combine their merits, and provide a more accurate estimation for location services. We have tested these three algorithm selectors with real data taken in Hong Kong. Experiment results have shown that they are all useful in particular, and the one with a Bayes probabilistic model outperforms all other existing location algorithms among different kinds of terrains in terms of average errors

关键词： Land mobile radio cellular systems Solid modeling Character generation Iterative algorithms Global Positioning System Mobile computing FCC Directive antennas Transmitting antennas Antennas and propagation

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Developing embedded Kernel for System-On-a-Chip Platform of Heterogeneous Multiprocessor Architecture

Developing Embedded Kernel for System-On-a-Chip Platform of ...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Jing Chen Jian-Hong Liu Department of Electrical Engineering National Cheng Kung University Tainan Taiwan

It has been common that modern embedded system products are built on platforms with system-on-a-chip (SOC) in which two or more different processor cores are put into one single chip and form the architecture of heterogeneous multiprocessor. Although providing high performance at low cost, such architecture brings new design challenges as well as increased complexity in developing embedded software especially at the level of kernel or operating system software. this paper presents our experience in developing an embedded microkernel that runs on embedded system of heterogeneous multiprocessor architecture composed of one general purpose processor (GPP) and one special purpose processor (SPP). Aside from following the traditional approach of monolithic operating system, the option of dual kernels based on microkernel architecture with uniform message-passing mechanism was taken to develop a symmetric embedded microkernel which can be compiled to run separately on each of the different processor cores in the system. the design and the approach not only reduce the software complexity in developing a kernel to manage different processors in a system but also enable a symmetric view from processors of different architectures. A prototype kernel was implemented on a reference design of Texas Instrument's TMS320DSC25 which is a heterogeneous multiprocessor SOC with a GPP of ARM7TDMI core and an SPP of C5409 DSP core

关键词： Kernel System-on-a-chip Computer architecture embedded system embedded software Operating systems Costs Software performance Software systems Software development management

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Evaluation of a new approach for the design of generic 4D guidance systems 13

Evaluation of a new approach for the design of generic 4D gu...

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13th Saint Petersburg international conference on Integrated Navigation systems, ICINS 2006

作者： Lu, W.C. Duan, L. Mora-Camino, F. Ouattara, B.O. ENAC LAAS du CNRS 7 avenue du Colonel Roche Toulouse31077 France ENAC UT2 7 venue Edouard Belin Toulouse31055 France ENAC LAAS du CNRS 7 avenue Edouard Belin Toulouse31055 France EAMAC ASECNA Niamey Nigeria

ISBN: (纸本)5900780627

Differential flatness, a property of some dynamic systems has made possible the development of new tools to analyze and to control complex nonlinear dynamic systems. Certain outputs presenting the flatness property are of special interest since it becomes possible, in theory by inverting the system dynamics, to derive from their planned trajectory the corresponding control inputs. Some papers have investigated the differential flatness of conventional aircraft full flight dynamics. In the case of air transportation, the sustained increase of air traffic during the last decades has led to severe saturation and environmental problems and new needs for aircraft guidance applications have appeared: traffic avoidance and relative guidance maneuvers, formation flight, continuous descent approaches, time metering and landing maneuvers. It has become more and more difficult to integrate these new complex functions within the classical discrete mode-based approach of guidance where complex trajectories are performed through the scheduling of elementary guidance modes. Until recently few works have been published by the flight control community to deal with what seems more profitable and safe in that case: a full trajectory-based approach of flight guidance. this communication is to propose an efficient trajectory-based guidance system with the help of flatness property of aircraft dynamics and neural networks. the proposed approach has been applied to the case of a general aviation aircraft where the inertial position of the aircraft is shown to be a differential flat output for its flight guidance dynamics. Since this differential flatness property is implicit as a result of the involved complex aerodynamic phenomena, a feed-forward neural network is built to deal with the inversion of the guidance dynamics. Once conveniently structured and trained, the neural network appears to be able to generate in real time the reference values to conventional autopilot systems concerne

关键词： Trajectories

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Deterministic Mechanism for Run-time Reconfiguration Activities in an RTOS

Deterministic Mechanism for Run-time Reconfiguration Activit...

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ieee international conference on Industrial Informatics (INDIN)

作者： Marcelo Gotz Florian Dittmann Carlos Eduardo Pereira Heinz Nixdorf Institute University of Paderborn Germany Electrical Engineering Department UFRGS Brazil

Reconfigurable computing based on hybrid architectures, comprising general purpose processor (CPU) and field programmable gate array (FPGA), is very attractive because it can provide high computational performance as well as flexibility to support the requirements of today's embedded systems. However, the relative high reconfiguration costs often are an obstacle when using such architectures for run-time reconfigurable systems. In order to still be able to benefit from the flexibility of such systems, the used real-time operating system must explicitly respect the reconfiguration time. In such systems, the reconfiguration activities need to be carried out during run-time without causing critical applications to miss their deadlines. In this paper, we show how we model these reconfiguration activities as aperiodic jobs. therefore, we apply the server-based method from the real-time scheduling theory to the scheduling of aperiodic activities. Using these techniques, we can achieve a deterministic environment for reconfiguration activities as well as an improvement of their responsiveness.

关键词： Runtime embedded computing High performance computing Computer architecture Field programmable gate arrays embedded system Costs real time systems Operating systems Delay

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Instruction Scheduling with Release times and Deadlines on ILP Processors

Instruction Scheduling with Release Times and Deadlines on I...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Hui Wu J. Jaffar Jingling Xue School of Computer Science and Engineering University of New South Wales Australia School of Computing National University of Singapore Singapore

ILP (instruction level parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimising compiler for ILP processors needs to find a feasible schedule for a set of time-constrained instructions. In this paper, we present a fast algorithm for scheduling instructions with precedence-latency constraints, individual integer release times and deadlines on an ILP processor with multiple functional units. the time complexity of our algorithm is O(n 2 logd)+min{O(de), O(ne)}+min{O(ne), O(n 2.376 )}, where n is the number of instructions, e is the number of edges in the precedence graph and d is the maximum latency. Our algorithm is guaranteed to find a feasible schedule whenever one exists in the following special cases: 1) one functional unit, arbitrary precedence constraints, latencies in {0,1}, integer release times and deadlines; 2) two identical functional units, arbitrary precedence constraints, latencies of 0, integer release times and deadlines; 3) multiple identical functional units or multiple functional units of different types, monotone interval-ordered graph, integer release times and deadlines; 4) multiple identical functional units, in-forest, equal latencies, integer release times and deadlines. In case 1) our algorithm improves the existing fastest algorithm from O(n 2 logn)+min{O(ne), O(n 2.376 )} to min{O(ne), O(n 2.376 )}. In case 2) our algorithm improves the existing fastest algorithm from O(ne+n 2 logn) to min{O(ne), O(n 2.376 )}. In case 3) no polynomial time algorithm for multiple functional units of different types was known before

关键词： Processor scheduling Delay Scheduling algorithm embedded system Timing Computer science Computer aided instruction embedded computing Optimizing compilers Polynomials

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Integrating Compiler and System Toolkit Flow for embedded VLIW DSP Processors

Integrating Compiler and System Toolkit Flow for Embedded VL...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Chi Wu Kun-Yuan Hsieh Yung-Chia Lin Chung-Ju Wu Wen-Li Shih S. C. Chen Chung-Kai Chen Chien-Ching Huang Yi-Ping You Jenq Kuen Lee Department of Computer Science National Tsing-Hua University Hsinchu Taiwan

To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constraints, distributed register files, variable-length encodings for instructions, and special data paths are frequently adopted. this creates challenges to deploy software toolkits for new embedded DSP processors. this article presents our methods and experiences to develop software and toolkit flows for PAC (parallel architecture core) VLIW DSP processors. Our toolkits include compilers, assemblers, debugger and DSP micro-kernels. We first retarget open research compiler (ORC) and toolkit chains for PAC VLIW DSP processor and address the issues to support distributed register files and ping-pong data paths for embedded VLIW DSP processors. Second, the linker and assembler are able to support variable length encoding schemes for DSP instructions. In addition, the debugger and DSP micro-kernel were designed to handle dual-core environments. the footprint of micro-kernel is also around 10K to address the code-size issues for embedded devices. We also present the experimental result in the compiler framework by incorporating software pipeline (SWP) policies for distributed register files in PAC architecture. Results indicated that our compiler framework gains performance improvement around 2.5 times against the code generated without our proposed optimizations

关键词： VLIW Digital signal processing Registers Encoding Software tools Assembly Application software embedded software Parallel architectures Pipelines

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