We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low level simulatio...
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ISBN:
(纸本)0769517129
We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low level simulation to understand the tradeoffs between energy, latency, and area. the domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. the high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration (DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection.
the explosive growth of embeddedsystems in existing and emerging application domains is accompanied by unique constraints and performance requirements along multiple dimensions such as speed, power, and real-time beh...
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ISBN:
(数字)9783540362654
ISBN:
(纸本)3540003037
the explosive growth of embeddedsystems in existing and emerging application domains is accompanied by unique constraints and performance requirements along multiple dimensions such as speed, power, and real-time behavior. Typically, these requirements are encapsulated in a few important components, or kernels, for example, for audio and video encoding/decoding, data compression, and encryption. Software implementations of these kernels executing on embedded microprocessors are inadequate to meet the requirements. Customization plays a central role in meeting these unique and specialized needs and has historically been realized by the development of custom hardware solutions such as fully custom application specific integrated circuits (ASICs).
However, each new generation of semiconductor technology is increasing the non- recurring engineering (NRE) costs associated with ASIC development and thereby making it feasible for only high volume applications and those with product lifetimes amenable to a long time to market design cycle. the increasing pervasiveness of embeddedsystems encompasses applications with smaller product lifetimes, shorter development cycles, and increasing cost containment pressures. Sustaining the continued growth demanded by the market will require technology to deliver performance characteristics of custom solutions while overcoming the twin hurdles of high NRE costs and long time to market of current ASIC solutions. Further, the embedded market is comprised of application segments covering a range of costs, volumes, and time to market needs. For example, components of 3G phones, set top boxes, color laser printers, color copiers, and network attached storage devices span a range of prices from on the order of a few hundred to a few thousand dollars and a range of volumes ranging from thousands to tens of millions of units. Consequently the approaches to customization are diverse.
the proceedings contain 22 papers. the topics discussed include: rapid prototyping of FPGA based floating point DSP systems;prototyping of fuzzy logic-based controllers using standard FPGA development boards;prototypi...
ISBN:
(纸本)076951703X
the proceedings contain 22 papers. the topics discussed include: rapid prototyping of FPGA based floating point DSP systems;prototyping of fuzzy logic-based controllers using standard FPGA development boards;prototyping of a high performance generic Viterbi decoder;prototyping Ethernet in the first mile over point-to-point copper;benefits of macro-based multi-FPGA partitioning for video processing applications;hybrid multi-FPGA board evaluation by limiting multi-hop routing;rapid prototyping of transition management code for reconfigurable control systems;reconfigurable hardware control software;interfacing software libraries from non-deterministic prototypes;validating object-oriented prototype of real-timesystems withtimed automata;and from object-oriented modeling to code generation for rapid prototyping of embedded electronic systems.
the proceedings contain 70 papers. the special focus in this conference is on High Performance computing. the topics include: High-performance computing and visualization;2-d wavelet transform enhancement on general-p...
ISBN:
(纸本)3540003037
the proceedings contain 70 papers. the special focus in this conference is on High Performance computing. the topics include: High-performance computing and visualization;2-d wavelet transform enhancement on general-purpose microprocessors;a general data layout for distributed consistency in data parallel applications;duplication-based scheduling algorithm for interconnection-constrained distributed memory machines;evaluating arithmetic expressions using tree contraction;a mechanism to reduce i-cache power consumption in high performance microprocessors;exploiting web document structure to improve storage management in proxy caches;high performance multiprocessor architecture design methodology for application-specific embeddedsystems;a low latency messaging infrastructure for Linux clusters;low-power high-performance adaptive computing architectures for multimedia processing;a technique to construct high performance CORBA applications;automatic search for performance problems in parallel and distributed programs by using multi-experiment analysis;an adaptive value-based scheduler and its RT-Linux implementation;effective selection of partition sizes for moldable scheduling of parallel jobs;runtime support for multigrain and multiparadigm parallelism;a fully compliant openMP implementation on software distributed shared memory;a fast connection-time redirection mechanism for internet application scalability;an efficient resource sharing scheme for dependable real-time communication in multihop networks;improving web server performance by network aware data buffering and caching;wraps scheduling and its efficient implementation on network processors;performance comparison of pipelined hash joins on workstation clusters and iterative algorithms on heterogeneous network computing.
Different successful heuristic approaches have been proposed for solving combinatorial optimization problems. Commonly, each of them is specialized to serve a different purpose or address specific difficulties. Howeve...
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ISBN:
(纸本)0769514170
Different successful heuristic approaches have been proposed for solving combinatorial optimization problems. Commonly, each of them is specialized to serve a different purpose or address specific difficulties. However, most combinatorial problems that model real world applications have a priori well known measurable properties. embedded machine learning methods may aid towards the recognition and utilization of these properties for the achievement of satisfactory solutions, In this paper we present a heuristic methodology which employs the instance-based machine learning paradigm, this methodology can be adequately configured for several types of optimization problems which are known to have certain properties. Experimental results are discussed concerning two well known problems, namely the knapsack problem and the set partitioning problem. these results show that the proposed approach is able to find significantly better solutions compared to intuitive search methods based on heuristics which are usually applied to the specific problems.
the correct behavior of real-timeapplications depends not only on the correctness of the results of computations but also on the times at which these results are produced. As a matter of fact, violations of real-time...
ISBN:
(纸本)3540423451
the correct behavior of real-timeapplications depends not only on the correctness of the results of computations but also on the times at which these results are produced. As a matter of fact, violations of real-time constraints in embeddedsystems are the most difficult errors to detect, because they are extremely sensitive both to the patterns of external events stimulating the system and to the timing behavior of the system itself. Clearly, the development of real-timesystems requires rigorous methods and tools to reduce development costs and “time-to-market” while guaranteeing the quality of the produced code (in particular, respect of the temporal constraints).
Different successful heuristic approaches have been proposed for solving combinatorial optimization problems. Commonly, each of them is specialized to serve a different purpose or address specific difficulties. Howeve...
详细信息
Different successful heuristic approaches have been proposed for solving combinatorial optimization problems. Commonly, each of them is specialized to serve a different purpose or address specific difficulties. However, most combinatorial problems that model real world applications have a priori well known measurable properties. embedded machine learning methods may aid towards the recognition and utilization of these properties for the achievement of satisfactory solutions. In this paper, we present a heuristic methodology which employs the instance-based machine learning paradigm. this methodology can be adequately configured for several types of optimization problems which are known to have certain properties. Experimental results are discussed concerning two well known problems, namely the knapsack problem and the set partitioning problem. these results show that the proposed approach is able to find significantly better solutions compared to intuitive search methods based on heuristics which are usually applied to the specific problems.
Java chip has been widely accepted in real-timeembeddedsystems. those embeddedapplications usually impose resource and real-time constraints on the design of CPU. In this paper;we seek a hardware-assisted scheme to...
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ISBN:
(纸本)0769509304
Java chip has been widely accepted in real-timeembeddedsystems. those embeddedapplications usually impose resource and real-time constraints on the design of CPU. In this paper;we seek a hardware-assisted scheme to support the runtime memory management and thus to provide real-time capability for embedded Java devices. We propose a dynamic garbage collection mechanism to guarantee predictable memory allocation time. the key point is that a co-processor identifies the data transition events in Java that memory management is accomplished by a circular heap. We show the design and architecture of the dynamic memory management in details. Our simulation results illustrate that the response time of memory allocation is much predictable, compared to other approaches.
the ever increasing complexity of embeddedsystems consisting of hardware and software components poses a challenge in verifying their correctness. New verification methods that overcome the limitations of traditional...
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ISBN:
(纸本)0769507654;0769507662
the ever increasing complexity of embeddedsystems consisting of hardware and software components poses a challenge in verifying their correctness. New verification methods that overcome the limitations of traditional techniques and, at the same time, are suitable for hardware/software systems are needed. In this work we formally define the semantics of PRES+, a Petri net based computational model aimed to represent embeddedsystems. We introduce an approach to formal verification of such systems: we make use of model checking to prove the correctness of embeddedsystems by determining the truth of CTL and TCTL formulas that specify required properties with respect to a PRES+ model. An ATM server illustrates the feasibility of our approach on practical applications.
To develop the applications for Internet appliances, embedded software development tools need various host tools such as cross compilers and binary utilities as well as a remote debugger, an interactive shell, and rea...
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ISBN:
(纸本)0769509304
To develop the applications for Internet appliances, embedded software development tools need various host tools such as cross compilers and binary utilities as well as a remote debugger, an interactive shell, and real-time resource monitors. the heavy host-target communication overhead and inconsistency caused by various host tools make target monitor programs more complex. In this paper, we propose a debugging protocol for these tools that supports several host-resident tools under the existence of RTOS. To abstract the details of the target systems, we have developed a target agent running as a task on the RTOS. Target agent is the counterpart of host agent that supports host tools through the communication over UDP/IP. the proposed architecture is implemented and tested on Esto (embeddedsystems Toolset), a development tool for Internet-based embeddedapplications.
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