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13th ieee international Symposium on Intelligent systems and Informatics (SISY)

作者： Struharik, R. Univ Novi Sad Fac Tech Sci Novi Sad 21000 Serbia

ISBN: (纸本)9781467393881

this paper presents four different architectures for the hardware acceleration of axis-parallel, oblique and non-linear decision tree ensemble classifier systems. Hardware architectures for the implementation of a number of ensemble combination rules are also presented. the proposed architectures are optimized for size, making them particularly interesting for embedded applications where the size of the system is critical constraint. Proposed architectures are suitable for the implementation using FPGA and ASIC technology. Experiment results obtained using 29 datasets from the standard UCI Machine Learning Repository database suggest that the FPGA implementations offer significant improvement in the classification time in comparison with the pure software implementations.

关键词： application specific integrated circuits decision trees electronic engineering computing field programmable gate arrays learning (artificial intelligence) pattern classification ASIC technology FPGA axis-parallel decision tree ensemble classifier systems decision tree ensemble hardware accelerators embedded applications ensemble combination rules hardware acceleration hardware architectures machine learning nonlinear decision tree ensemble classifier systems oblique decision tree ensemble classifier systems Acceleration Computer architecture Decision trees Hardware Pipelines Registers Software Field programmable gate arrays embedded application Decision Trees application specific integrated circuits electronic engineering computing Computer Architecture Registers Computer hardware Pattern recognition pipeline acceleration computer software hardware architecture

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Scalable embedded systems: Towards the Convergence of High-Performance and embedded computing 13

Scalable Embedded Systems: Towards the Convergence of High-P...

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13th international conference on embedded and Ubiquitous computing (EUC 2015)

作者： Giorgi, Roberto Univ Siena Siena Italy

ISBN: (纸本)9781467382991

embedded System toolchains are highly customized for a specific System-on-Chip (SoC). When the application needs more performance, the designer is typically forced to adopt a new SoC and possibly another toolchain. the rationale for not scaling performance by using, e.g., two SoCs, is that maintining most of the operations on-chip may allow for higher energy efficiency. We are exploring the feasibility and trade-offs of designing and manufacturing a new Single Board Computer (SBC) that could serve flexibly for a number of current and future applications, by allowing scalability through clusters of SBCs while keeping the same programming model for the SBC. this board is based on FPGAs and embedded processors, and its key points are: i) a fast custom interconnect for board-to-board communication and ii) an easily programmable environment which would allow both the off-loading of code into accelerators (either soft-IP blocks or hard-IP blocks) and, at the same time, the distribution of computation across boards. A key challenge to successfully deploying this paradigm is to properly distribute the threads across several boards without the explicit intervention of the programmer. In this paper we describe how to dynamically and efficiently distribute the computational threads in symbiosis with an appropriate memory model to allow the system scalability, so that we can double the performance by simply connecting two boards without i) changing the basic hardware components (e.g., to a different System-On-Chip) and ii) changing the programming model to follow the vendor specific toolchain. Our approach is to reduce data movement across boards. Our initial experiments have confirmed the feasibility of our approach.

关键词： Cyber-Physical systems Reconfigurable systems Cluster Programming FPGA Programming Distributed Shared Memory Programming Model Performance Evaluation

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Proceedings - ieee/IFIP 13th international conference on embedded and Ubiquitous computing, EUC 2015

Proceedings - IEEE/IFIP 13th International Conference on Emb...

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13th ieee/IFIP international conference on embedded and Ubiquitous computing, EUC 2015

ISBN: (纸本)9781467382991

the proceedings contain 30 papers. the topics discussed include: exploring embedded symmetric multiprocessing with various on-chip architectures;fast and scalable thread migration for multi-core architectures;semi-partitioned scheduling of fork-join tasks using work-stealing;evaluation of a systematic approach in variant management for safety-critical systems development;lua-based virtual machine platform for spacecraft on-board control software;pattern-based approach for designing fail-operational safety-critical embedded systems;architecture-driven development approach for WSAN applications;context aware power management enhanced by radio wake up in body area networks;scalable simulation of wireless electro-magnetic nanonetworks;and offloading of web application computations: a snapshot-based approach.

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embedded computing Technology for Highly-demanding Cyber-physical systems 13

Embedded Computing Technology for Highly-demanding Cyber-phy...

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13th IFAC and ieee conference on Programmable Devices and embedded systems

作者： Jozwiak, Lech Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands

the recent spectacular progress in the microelectronic, information, communication, material and sensor technologies created a big stimulus towards development of much more sophisticated, coherent and fit to use, smart communicating cyber-physical systems (CPS). the huge and rapidly developing markets of the modern CPS represent great opportunities for both private enterprises and country economies. However, these opportunities come with a price of unusual systems complexity. as well as, stringent and difficult to satisfy requirements of the modern CPS applications. Specifically, numerous mobile and autonomous CPS applications require a. o. a guaranteed (ultra-)high performance or (ultra-)low energy consumption, as well as, a high reliability, safety and security. To adequately address these problems and overcome the related challenges a sophisticated embedded computing and embedded design technologies are needed. After a brief introduction to modern CPS and consideration of several serious challenges of their design, this paper discusses the embedded computing technology needed for the modern complex and highly-demanding mobile and autonomous CPS. (C) 2015, IFAC (international Federation of Automatic Control) Hosting by Elsevier Ltd. Ail rights reserved.

关键词： cyber-physical systems embedded processors application-specific processors multiprocessor system on a chip (MPSoC) mobile systems autonomous systems smart wearables smart cars video and image processing high performance low energy consumption

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Cognitive RF Stealth Radar Using Spoiled Weighting Vector For Doppler Compensation

Cognitive RF Stealth Radar Using Spoiled Weighting Vector Fo...

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2016 ieee 13th international conference on Signal Processing（ICSP2016）

作者： Zhe Wang Yi-Sheng Yan Jie Xiong IEEE

this paper proposes a cognitive radio frequency(RF) stealth radar using phased array(PA) for surveillance applications. Since the traditional surveillance systems are accessible by intercept receivers, the series of low-gain beam is used to reduce the visibility of this system. the traditional highgain PA antenna beam is replaced by the novel beam. And the original detection performance isnot degraded. Furthermore, we combine cognitive radar with these low-gain beam to update current operation parameters, the update scheme of closedloop adaptively is denoted to real-time update this weighting vector for aiming to the target and compensating the Doppler shifter. through the simulation results,this paper confirms all the methods these were proposed.

关键词： RF stealth Cognitive radar low probability of intercept surveillance systems

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High Level Model of time Predictable Multitask Control Unit 13

High Level Model of Time Predictable Multitask Control Unit

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13th IFAC and ieee conference on Programmable Devices and embedded systems

作者： Golly, Lukasz Milik, Adam Pulka, Andrzej Silesian Tech Univ Inst Elect Dept Automat Control Elect & Comp Sci Ul Akad 16 Gliwice Poland

the paper describes the high level abstract SystemC model of the multitask real time system. the authors put their main effort to obtain the highly time predictable system. the time predictability of real time embedded, electronic systems is identified and a concise survey of various approaches to the problem arc given. the architecture of a single pipeline processor core with thread interleaving mechanism is emphasized. the scheduling algorithms that enable optimal utilization of the processing units arc illustrated on examples. the main memory access control unit and the original memory system organization arc described. Many simulation experiments conducted with single and multi-core system architecture implementation, allow obtaining results that prove advantages of the presented model. (C) 2015, IFAC (international Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： real-time systems embedded systems Multiprocessing systems Pipelining processing Parallelism Concurrency Multithreading and multitasking time predictable machines

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Formal Synthesis of Optimal RTOS 17

Formal Synthesis of Optimal RTOS

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2015 ieee 17th international conference on High Performance computing and Communications (HPCC)

作者： Kabland, Toussaint Gautier Tigori Bechennec, Jean-Luc Roux, Olivier Henri IRCCyN CNRS UMR 6597 1Rue Noe BP92101 F-44321 Nantes 3 France

ISBN: (纸本)9781479989379

the adaptation of an operating system to an application is often needed to optimize the embedded code. Adaptation consists in removing the unneeded operating systems services and the dead code according to applications requirements. the resulting stripped operating system is smaller, safer and has better performance. this adaptation is usually done by hand for each application. As a result some dead code may remain unnoticed. the verification and the certification of the adapted operating system is difficult too: for each adaptation to an application, the certification must be redone and for the verification, a new model has to be designed with the well known gap problem between the model and the actual software. In this paper, we present a new approach based on formal methods to synthesize an Application-Specific real-time Operating System. Instead of removing services from the source code of an existing operating system, a formal model is used. All the functions of the operating system with the full control flow and control variables are modeled. According to an application model, unneeded services and part of control flow are removed from the model by using a reachability analysis. this guarantees no dead code remains. Moreover some properties may be checked on the pruned model to ensure the application behaves as expected. At last, the corresponding source code is generated from the model.

关键词： certification formal verification operating systems (computers) reachability analysis source code (software) application model application-specific real-time operating system control flow control variables embedded code formal synthesis method operating system certification operating system verification optimal RTOS source code stripped operating system Adaptation models Automata Cost accounting Memory management Object oriented modeling Operating systems real-time systems Formal Methods real-time Operating systems Synthesis reachability analysis Operating systems Source code real time operating system Object oriented modeling cost accounting certification Store management Formal verification real-time systems Automata embedded encoding synthesis

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Ray-tracing domain decomposition methods for real-time simulation on multi-core and multi-processor systems

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2016年第16期28卷 4352-4364页

作者： Magoules, Frederic Gbikpi-Benissan, Guillaume Callet, Patrick Technol Res Inst SystemX 8 Ave Vauve F-91120 Palaiseau France CentraleSupelec F-92295 Chatenay Malabry France

this paper describes the use of domain decomposition methods for accelerating wave physics simulation. Numerical wave-based methods provide more accurate simulation than geometrical methods, but at a higher computation cost as well. In the context of virtual reality, the quality of the results is estimated according to human perception, what makes geometrical methods an interesting approach for achieving real-time physically-based rendering. Here, we investigate a geometrical method based on both beams and rays tracing, which we enhance by two levels of parallel processing. Techniques from domain decomposition methods are coupled with classical parallel computing on both shared and distributed memory. Both optic and acoustic renderings are experimented to evaluate the acceleration impact of the domain decomposition scheme. Speedup measurements clearly show the efficiency of using domain decomposition methods for real-time simulation of wave physics. Copyright (C) 2015 John Wiley & Sons, Ltd.

关键词： ray-tracing beam-tracing parallel computing domain decomposition method wave propagation acoustic optic

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real-time parallel implementation of road traffic radar video processing algorithms on a parallel architecture based on DSP and ARM processors 15

Real-time parallel implementation of road traffic radar vide...

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15th international conference on Intelligent systems Design and applications (ISDA)

作者： Klilou, Abdessamad Bourzeix, Francois Bourja, Omar Zennayi, Yahya Mabrouk, Lhoussein Belkouch, Said Moroccan Fdn Adv Sci Innovat & Res MAScIR Embedded Syst Dept Rabat Morocco Univ Cadi Ayyad Ecole Natl Sci Appl Marrakech Morocco

ISBN: (纸本)9781467387095

Machine vision algorithms require high-computing power. A high performance parallel system has been proposed in this paper by implementing a road traffic radar video processing chain in real-time on a new embedded architecture. the proposed machine consists of the Digital Signal Processor (DSP) 66AK2H12 from Texas Instruments (TI). the goal of this paper is the estimation of the vehicles number, speeds and classification through an optimal exploitation of the parallel architecture based on DSP and ARM cores and high speed buses used in the video acquisition and processing.

关键词： road traffic radar video processing real-time processing parallel architecture

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Power Management in Cluster-Based Energy-Harvesting Sensor Networks through Dynamic Modulation Scaling 17

Power Management in Cluster-Based Energy-Harvesting Sensor N...

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2015 ieee 17th international conference on High Performance computing and Communications (HPCC)

作者： Bandari, Maryam Simon, Robert Aydin, Hakan George Mason Univ Dept Comp Sci Fairfax VA 22030 USA

ISBN: (纸本)9781479989379

this paper considers real-time cluster-based wireless sensor networks where the nodes harvest energy from the environment. We target performance sensitive applications that have to collectively send their information to cluster head by a predefined deadline, such as in distributed real-time monitoring and detection. the nodes are equipped with Dynamic Modulation Scaling (DMS) capable wireless radios. the problem is to determine the time slots and modulation levels that will be used by each node while communicating with the cluster-head in order to achieve energy-neutral (perpetual) operation and maximize energy reserves. We propose a solution that adjusts underlying TDMA slots to enable high-energy nodes to transmit faster and thus produce larger slack for low-energy nodes, while meeting the performance constraint. We present an optimal mixed integer programming based solution. We also develop fast heuristics that are shown to provide approximate solutions through comprehensive experiments with actual solar energy harvesting profiles.

关键词： energy harvesting integer programming modulation pattern clustering telecommunication power management wireless sensor networks DMS TDMA cluster-based energy-harvesting wireless sensor network dynamic modulation scaling energy-neutral operation optimal mixed integer programming power management solar energy harvesting profile wireless radio Batteries Energy harvesting Logic gates Modulation real-time systems Wireless communication Wireless sensor networks

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