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Wear-Leveling for PCM Main Memory on embedded System via Page Management and Process Scheduling 20

Wear-Leveling for PCM Main Memory on Embedded System via Pag...

引用

20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Pan, Chen Xie, Mimi Hu, Jingtong Qiu, Meikang Zhuge, Qingfeng Oklahoma State Univ Sch Elect & Comp Engn Stillwater OK 74078 USA San Jose State Univ Dept Comp Engn San Jose CA 95192 USA Chongqing Univ Coll Comp Sci Chongqing 630044 Peoples R China

ISBN: (纸本)9781479939534

Phase Change Memory (PCM) has been considered as a leading candidate to replace the traditional DRAM in embedded systems due to its promising characteristics such as low leakage power, low cost, non-volatility, and high scalability. One of the constraints that undermine the credential of PCM as main memory is its limited write endurance. In this paper, we develop wear-leveling techniques purely on the Operating System (OS) level to extend lifetime of PCM. Without extra hardware support, OS management is more flexible to be integrated into existing embedded systems. To achieve wear-leveling, the Periodical Page Swapping (PPS), Rearrangement Inequality Based Page Allocation (RIPA), and Write Intensity Based Process Scheduling (WIPS) algorithms are proposed in this paper on OS level. the experimental results show that the proposed techniques can significantly extend the lifetime of PCM main memory.

关键词： Phase Change Memory lifetime wear-leveling operating system

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Efficient Online Benefit-Aware Multiprocessor Scheduling Using an Online Choice of Approximation Algorithms 16

Efficient Online Benefit-Aware Multiprocessor Scheduling Usi...

引用

16th ieee Int Conf on High Performance computing and Communications/11th ieee Int Conf on embedded Software and systems\6th Int Symposium on Cyberspace Safety and Security

作者： Sanati, Behnaz Cheng, Albert M. K. Univ Houston Dept Comp Sci Real Time Syst Lab Houston TX 77004 USA

ISBN: (纸本)9781479961238

Maximizing the benefit gained by soft real-time jobs in many applications and embedded systems is highly needed to provide an acceptable QoS (Quality of Service). this paper considers a benefit model for on-line preemptive multiprocessor scheduling. the goal is to maximize the total benefit gained by the jobs that meet their deadlines. this method prioritizes the jobs using their benefit density functions and schedules them in a real-time basis. We propose an online choice of two approximation algorithms in order to partition the jobs among identical processors at the time of their arrival without using any statistics. Our analysis and experiments show that we are able to maximize the gained benefit and decrease the computational complexity (compared to existing algorithms) while minimizing make span (response time, also referred to as cost), with fewer missed deadlines and more balanced usage of processors. Our solution is applicable to a wide variety of soft real-time applications and embedded systems such as, but not limited to multimedia applications, medical monitoring systems or those with higher utilization such as bursty hosting servers.

关键词： Multiprocessor Online Scheduling embedded Make span Benefit Greedy Load-balancing Partitioning Preemptive

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CCM: Low Cost Dynamic data Exchange to Emulate RAM on NAND Flash 20

CCM: Low Cost Dynamic data Exchange to Emulate RAM on NAND F...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Zhao, Junhua Wu, Hejun Zhao, Yongjian Liu, Weiwei Sun Yat Sen Univ Sch Informat Sci & Technol Dept Comp Sci Guangzhou 510275 Guangdong Peoples R China

ISBN: (纸本)9781479939534

In embedded systems, it brings great benefits to use NAND flash for dynamic data exchange like using RAM, since RAM is usually expensive and consumes much energy. However, the major hardware limitations of NAND flash make it difficult to directly and dynamically read\write\erase on NAND flash. Traditional virtual memory systems are all based on flash translation layer and file system, which lead to frequently flash read\write\erase and more RAM requirement. To address this problem, we propose a Comet Circle Model (CCM) to emulate RAM for low cost embedded systems in this paper. CCM dynamically makes the distribution of valid pages in NAND flash follow a fixed function through integrating its physical page-level mapping and circularly write-back techniques. As a result, CCM can select a block without valid pages to write data almost every time in data writing, which avoids data moving among blocks. Both theoretical analysis and experimental results show that the data moving times and erase counts of CCM closely reach the theoretical lower bounds.

关键词： embedded systems real-time systems NAND flash memory Comet Circle model (CCM) dynamic data exchange virtual memory system Least Recently Used (LRU)

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Effects of Structured Parallelism by Parallel Design Patterns on embedded Hard real-time systems 20

Effects of Structured Parallelism by Parallel Design Pattern...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Jahr, Ralf Gerdes, Mike Ungerer, theo Ozaktas, Haluk Rochange, Christine Zaykov, Pavel G. Univ Augsburg D-86159 Augsburg Germany Univ Toulouse 3 F-31062 Toulouse France Honeywell Int Sro Brno Czech Republic

ISBN: (纸本)9781479939541

Parallel multi-threaded applications are needed to gain advantage from multi-and many-core processors. Such processors are more frequently considered for embedded hard real-time with defined timing guarantees, too. the static timing analysis, which is one way to calculate the worst-case execution time (WCET) of parallel applications, is complex and time-consuming due to the difficulty to analyze the interferences of threads and the high annotation effort to resolve it. Structured parallelism by a defined set of timing analyzable Parallel Design Patterns (PDPs) and Synchronization Idioms (SIs) is proposed in this paper for the development of hard real-time parallel applications. this enables static WCET analysis, reduces the necessary annotation effort, and leads to more accurate WCET estimates. We evaluate the impact of such structured parallelism in an industrial case study with an avionics application. A comparison of an existing implementation optimized for average-case performance (AC version) and a modified implementation taking into account timing analyzable PDPs and SIs (TA version) is made. the results demonstrate low variation in the measured average-case performance for up to eight threads running on eight cores. However, the annotation effort for the static WCET analysis of the TA version is significantly reduced (by up to 87.5%). In addition, the WCET speedup for the TA version is up to 172% (for 16 threads) higher compared to the speedup of the AC version.

关键词： Message systems Parallel processing Pipelines real-time systems Software Synchronization Computer based information systems real-time systems PARALLEL PROCESSING (COMPUTERS) pipeline computer software hard real-time system piping parallel design design pattern thREADS

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the Trajectory approach for AFDX FIFO networks revisited and corrected 20

The Trajectory approach for AFDX FIFO networks revisited and...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Li, Xiaoting Cros, Olivier George, Laurent ECE Paris LACSC F-75015 Paris France Univ Paris Est LIGM F-77454 Champs Sur Marne France

ISBN: (纸本)9781479939541

We consider the problem of dimensioning real-time AFDX FIFO networks with a worst-case end-to-end delay analysis. the state-of-the-art has considered several approaches to compute these worst-case end-to-end delays. Among them, the Trajectory approach has received more attention as it has been shown to provide tight end-to-end delay upper bounds. Recently, it has been proved that current Trajectory analysis can be optimistic for some corner cases, leading in its current form, to certification issues. In this paper, we first characterize the source of optimism in the Trajectory approach on detailed examples. then, we provide a correction to the identified problems. Two problems are solved: the first one is on the root cause of the underestimated time interval to compute delays of competing flows and a problem in the definition of the end-to-end delay computation. the second one is on the way that serialized frames are taken into account in the worst-case delay analysis.

关键词： Delays Ethernet networks Ports (Computers) real-time systems Switches Trajectory Upper bound Ethernet networks trajectory Upper bound real-time systems Switches delay first-in first-out End-to-end delay TRAJECTORY ANALYSIS

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Optimal Semi-Partitioned Scheduling in Soft real-time systems 20

Optimal Semi-Partitioned Scheduling in Soft Real-Time System...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Anderson, James H. Erickson, Jeremy P. Devi, UmaMaheswari C. Casses, Benjamin N. Univ N Carolina Dept Comp Sci Chapel Hill NC 27515 USA IBM Res India New Delhi India

ISBN: (纸本)9781479939541

Semi-partitioned real-time scheduling algorithms extend partitioned ones by allowing a (usually small) subset of tasks to migrate. the first such algorithm to be proposed was directed at soft real-time (SRT) sporadic task systems where bounded deadline tardiness is acceptable. that algorithm, called EDF-fm, has the desirable property that migrations are boundary-limited, i.e., they can only occur at job boundaries. However, it is not optimal because per-task utilization restrictions are required. In this paper, a new optimal semi-partitioned scheduling algorithm for SRT sporadic task systems is proposed that eliminates such restrictions. this algorithm, called EDF-os, preserves the boundary-limited property. In overhead-aware schedulability experiments presented herein, EDF-os proved to be better than all other tested alternatives in terms of schedulability in almost all considered scenarios. It also proved capable of ensuring very low tardiness bounds, which were near zero in most considered scenarios.

关键词： Algorithm design and analysis Program processors real-time systems Resource management Schedules Scheduling algorithms Algorithm design and analysis Program processors Scheduling algorithms real-time systems soft real-time system management of resources

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Energy-Efficient Allocation of real-time applications onto Heterogeneous Processors 20

Energy-Efficient Allocation of Real-Time Applications onto H...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Colin, Alexei Kandhalu, Arvind Rajkumar, Ragunathan (Raj) Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

ISBN: (纸本)9781479939541

Self-powered vehicles that interact with the physical world, such as spacecraft, require computing platforms with predictable timing behavior and a low energy demand. Energy consumption can be reduced by choosing energy-efficient designs for both hardware and software components of the platform. We leverage the state-of-the-art in energy-efficient hardware design by adopting Heterogeneous Multi-core Processors with support for Dynamic Voltage and Frequency Scaling and Dynamic Power Management. We address the problem of allocating real-time software components onto heterogeneous cores such that total energy is minimized. Our approach is to start from an analytically justified target load distribution and find a task assignment heuristic that approximates it. Our analysis shows that neither balancing the load nor assigning all load to the "cheapest" core is the best load distribution strategy, unless the cores are extremely alike or extremely different. the optimal load distribution is then formulated as a solution to a convex optimization problem. A heuristic that approximates this load distribution and an alternative method that leverages the solution explicitly are proposed as viable task assignment methods. the proposed methods are compared to state-of-the-art on simulated problem instances and in a case study of a soft-real-time application on an off-the-shelf ARM big. LITTLE heterogeneous processor.

关键词： Energy efficiency Energy efficiency Load distribution real-time application program core computer hardware design PROCESSOR Leverage Arts LOAD Spacecraft

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Non-volatile Registers Aware Instruction Selection for embedded systems 20

Non-volatile Registers Aware Instruction Selection for Embed...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Xie, Mimi Pan, Chen Hu, Jingtong Xue, Chun Jason Zhuge, Qingfeng Oklahoma State Univ Sch Elect & Comp Engn Stillwater OK 74078 USA City Univ Hong Kong Dept Comp Sci Kowloon Hong Kong Peoples R China Chongqing Univ Coll Comp Sci Chongqing 630044 Peoples R China

ISBN: (纸本)9781479939534

It is common that embedded systems are powered by limited and unstable power supply. In order to improve the reliability of embedded systems against unstable power supply, non-volatile memory (e.g. FRAM) based registers are proposed for embedded processors. FRAM-based registers have many advantages over traditional CMOS-based volatile registers such as non-volatility and power-economy. However, similar to other non-volatile memories (NVM), write operations to FRAM consume more time and power compared with read operations and limit the lifetime of the registers. Existing compiler optimization techniques never take the writes to registers into consideration. therefore, code generated by a traditional compiler has an adverse effect on processors with non-volatile registers. this paper aims at improving the lifetime and efficiency of non-volatile registers based embedded processors by generating NV register friendly code. To achieve the goal, in this paper, we investigate the usage of memory access instructions and propose the NV Register Aware Instruction Selection (NAIS) algorithm to reduce the write operations on non-volatile registers. According to the experimental results, the proposed algorithm can reduce the writes on NV registers by 66.89% on average when compared with GCC [1]. thus the lifetime of NV registers is extended to 2 times as long as before on average. the time cost is reduced by 56.68% and the energy consumption is reduced by 59.76% on average.

关键词： Ferroelectric RAM

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Operating System Support to an Online Hardware-Software Co-Design Scheduler for Heterogeneous Multicore Architectures 20

Operating System Support to an Online Hardware-Software Co-D...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Bueno, Maikon A. F. de Holanda, Jose A. M. Pereira, Erinaldo Marques, Eduardo Univ Sao Paulo Inst Math & Comp Sci Sao Carlos SP Brazil

ISBN: (纸本)9781479939541

this paper aims at designing and implementing a scheduler model for heterogeneous multiprocessor architectures based on software and hardware. As a proof of concept, the scheduler model was applied to the Linux operating system running on the SPARe Leon3 processor. In this sense, performance monitors have been implemented within the processors, which identify demands of processes in real-time. For each process, its demand is projected for the other processors in the architecture and then, it is performed a balancing to maximize the total system performance by distributing processes among processors. the Hungarian maximization algorithm, used in balancing scheduler was developed in hardware, and provides greater parallelism and performance in the execution of the algorithm. the scheduler has been validated through the parallel execution of several benchmarks, resulting in decreased execution times compared to the scheduler without the heterogeneity support.

关键词： Benchmark testing Integrated circuits Monitoring Benchmark testing scheduler program PROCESSOR MULTIPROCESSOR ARCHITECTURE Computer hardware System performance Integrated circuits Electronic circuits ARCHITECTURE Support systems parallel execution Legal Executions Co-design Operating systems

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Optimal and fast composition of resource-sharing components in hierarchical real-time systems 20

Optimal and fast composition of resource-sharing components ...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： van den Heuvel, M. M. H. P. Behnam, M. Bril, R. J. Lukkien, J. J. Nolte, T. Tech Univ Eindhoven NL-5612 AZ Eindhoven Netherlands Malardalen Real Time Res Ctr MRTC SE-72123 Vasteras Sweden

ISBN: (纸本)9781479939541

In this paper we consider various flavors of the stack resource policy (SRP) for arbitrating access to shared resources in a hierarchical scheduling framework (HSF) upon a uni-processor. We propose algorithms for exploring and selecting the (local) resource ceilings within components, such that it results in an optimal composition of resource-sharing components in an HSF. Existing methods are non-optimal, because (i) they optimize just the length of global non-preemptive execution of tasks and (ii) they do not detect whether or not resources are shared globally (i.e., between tasks of different components). Lifting these limitations leads to an exponential growth of the design space. this paper contributes a fast three-step methodology which lifts these limitations, i.e., we apply the SRP at each level of the HSF to just the resources being shared. Our algorithm selects those component interfaces (i.e., by fixing the local resource ceilings of each component) that minimize the system load.

关键词： Algorithm design and analysis Processor scheduling Protocols real-time systems Resource management Synchronization Algorithm design and analysis real-time systems scheduling of multiprocessor management of resources protocols Interleukin-6 Signal Recognition Particle Religious Missions Optimal Ceilings ceilings

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