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检索条件"任意字段=13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications"

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Multi-objective aware design flow for coarse-grained systems on chip 20

Multi-objective aware design flow for coarse-grained systems...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Chen, Peng Wang, Chao Li, Xi Zhou, Xuehai Univ Sci & Technol China Dept Comp Sci Hefei 230026 Anhui Peoples R China

ISBN: (纸本)9781479939534

this paper presents a software and hardware co-design flow for the coarse-grained systems on chip. It enables a multi-target design space exploration (MT-DSE) algorithm with multiple objectives such as chip area utilization, energy consumption, core efficiency, interconnection structure, application workload and speedup aware. With the help of the MT-DSE tool, the proposed design flow can supply a valuable assistance for architecture designers to develop a well trade-off multi-processor system. In contrast, most of state-of-the-art design space exploration tools rely on varieties of simulations or implementations that are quite time-consuming. Benefit from no such dependences, the MT-DSE method could turn out the optimized alternative very fast with multiple factors balanced. Besides, the tool is employed at a very early stage in the component based systems design and only needs a little profiling information which can greatly reduce the development term of the design. As an illustration, the JPEG compression algorithm is chosen to demonstrate how the tool exploits a given application and guides to build the most desired architecture.

关键词： coarse-grained system DSE multiple objectives MPSoC

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Digital Trust - Trusted computing and Beyond A Position Paper 13

Digital Trust - Trusted Computing and Beyond A Position Pape...

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13th ieee international conference on Trust Security and Privacy in computing and Communications (TrustCom)

作者： Akram, Raja Naeem Ko, Ryan K. L. Univ Waikato Dept Comp Sci Cyber Secur Lab Hamilton New Zealand

ISBN: (纸本)9781479965137

Along with the invention of computers and interconnected networks, physical societal notions like security, trust, and privacy entered the digital environment. the concept of digital environments begins with the trust (established in the real world) in the organisation/ individual that manages the digital resources. this concept evolved to deal with the rapid growth of the Internet, where it became impractical for entities to have prior offline (real world) trust. the evolution of digital trust took diverse approaches and now trust is defined and understood differently across heterogeneous domains. this paper looks at digital trust from the point of view of security and examines how valid trust approaches from other domains are now making their way into secure computing. the paper also revisits and analyses the Trusted Platform Module (TPM) along with associated technologies and their relevance in the changing landscape. We especially focus on the domains of cloud computing, mobile computing and cyber-physical systems. In addition, the paper also explores our proposals that are competing with and extending the traditional functionality of TPM specifications.

关键词： cloud computing computer network security data privacy mobile computing trusted computing Internet TPM specifications cyberphysical systems digital resource management digital trust evolution heterogeneous domains interconnected networks physical societal notions secure computing trusted platform module Computer architecture Computers Engines Mobile communication Proposals Security Semantic Web Cloud computing Cyber-Physical System embedded Devices Provenance Smart Cards Trust Trusted computing Cloud computing Mobile computing Trust Nonprofit Organizations trust Network security Health Smart Cards Computers Data privacy Computer Architecture Cyber-physical systems Trusted Platform Module Engines mobile communication semantic networks

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Component-Based Analysis of Hierarchical Scheduling using Linear Hybrid Automata 20

Component-Based Analysis of Hierarchical Scheduling using Li...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Sun, Youcheng Lipari, Giuseppe Soulat, Romain Fribourg, Laurent Markey, Nicolas Scuola Super Sant Anna Pisa Italy ENS Cachan LSV Cachan France CNRS F-75700 Paris France

ISBN: (纸本)9781479939541

Formal methods (e.g. timed Automata or Linear Hybrid Automata) can be used to analyse a real-time system by performing a reachability analysis on the model. the advantage of using formal methods is that they are more expressive than classical analytic models used in schedulability analysis. For example, it is possible to express state-dependent behaviour, arbitrary activation patterns, etc. In this paper we use the formalism of Linear Hybrid Automata to encode a hierarchical scheduling system. In particular, we model a dynamic server algorithm and the tasks contained within, abstracting away the rest of the system, thus enabling component-based scheduling analysis. We prove the correctness of the model and the decidability of the reachability analysis for the case of periodic tasks. then, we compare the results of our model against classical schedulability analysis techniques, showing that our analysis performs better than analytic methods in terms of resource utilisation. We further present two case studies: a component with state-dependent tasks, and a simplified model of a real avionics system. Finally, through extensive tests with various configurations, we demonstrate that this approach is usable for medium-size components.

关键词： Analytical models Automata Heuristic algorithms Partitioning algorithms Processor scheduling real-time systems Servers Hybrid automata real-time systems Partitioning algorithms scheduling of multiprocessor Servers Heuristic algorithms reachability analysis Automata ANALYSIS MODELS Religious Missions timed automata

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Energy efficient real-time task scheduling for embedded systems with hybrid main memory 20

Energy efficient real-time task scheduling for embedded syst...

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20th ieee international conference on embedded and real-time computing systems and applications, RTCSA 2014

作者： Zhang, Zhiyong Liu, Peng Ju, Lei Jia, Zhiping School of Computer Science and Technology Shandong University Jinan China

ISBN: (纸本)9781479939534

Available energy is the most critical limitation on the performance of embedded systems along with the increasing sophistication. Phase Change Memory (PCM), with high density and low idle power has recently been extensively studied as a promising alternative main memory of DRAM. In this paper, a hybrid PCM/DRAM main memory is utilized to leverage the low power of PCM and high performance of DRAM. We reconsider the real-time task scheduling problem of hybrid PCM/DRAM-based embedded systems. To maximize energy saving, two static scheduling algorithms under Rate-Monotonic(RM) and Earliest Deadline First (EDF) are proposed while guaranteeing the real-time constraints of all tasks. Since the actual execution time is much shorter than the worst-case execution time in real environment, we propose two dynamic mechanisms to optimize the energy consumption of our static solutions, so as to fully use the slack time produced by completed tasks. All the proposed algorithms minimize the number of task migrations from PCM to DRAM and ensure each task instance can be migrated at most once. Experimental results show our real-time scheduling algorithms reduce 25.7% to 47.2% of energy consumption on average. © 2014 ieee.

关键词： Scheduling algorithms

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Accelerating Genome Assembly using Hard embedded Blocks in FPGAs

Accelerating Genome Assembly using Hard Embedded Blocks in F...

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27th international conference on VLSI Design / 13th international conference on embedded systems (VLSID)

作者： Varma, B. Sharat Chandra Paul, Kolin Balakrishnan, M. Indian Inst Technol Delhi Dept Comp Sci & Engn New Delhi 110016 India

ISBN: (纸本)9781479925124

Modern FPGAs consist of a number of Hard embedded Blocks (HEBs) like BRAMs, DSPs, PCI controllers, etc. for performing specialized operations/functions. this helps in developing efficient architectures for accelerating compute intensive kernels. Computational genomics is a fairly recent domain which helps in the understanding of the biological properties of an organism with applications in medicine, evolutionary biology and social sciences. A key problem in this research domain is the assembly of DNA sequences obtained from sequencing machines. Next Generation DNA Sequencing (NGS) technologies generate a large number of short fragments (sequences) of fixed length known as reads, which are a part of the genome sequence being assembled. It is computationally very time consuming to assemble these short reads to form the genome sequence purely with software. FPGAs have been effectively used to build accelerators to speed up the computation process. In this paper, we propose HEBs to accelerate the genome assembly process. We show 20% increase in speedups using FPGAs with HEBs over existing FPGA implementation. Speedups of up-to 11x can be obtained over Velvet [1] which is a commonly used software implementation.

关键词： FPGA based Acceleration Genome Assembly Hard embedded Blocks NGS assembly

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Reduced Buffering Solution for Multi-Hop HaRTES Switched Ethernet Networks 20

Reduced Buffering Solution for Multi-Hop HaRTES Switched Eth...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Ashjaei, Mohammad Behnam, Moris Pedreiras, Paulo Bril, Reinder J. Almeida, Luis Nolte, thomas Malardalen Univ MRTC Vasteras Sweden Univ Aveiro IT DETI P-3800 Aveiro Portugal Univ Porto IT DEEC P-4100 Oporto Portugal Tech Univ Eindhoven Eindhoven Netherlands

ISBN: (纸本)9781479939541

In the context of switched Ethernet networks, multihop communication is essential as the networks in industrial applications comprise a high amount of nodes, that is far beyond the capability of a single switch. In this paper, we focus on multi-hop communication using HaRTES switches. the HaRTES switch is a modified Ethernet switch that provides real-time traffic scheduling, dynamic Quality-of-Service and temporal isolation between real-time and non-real-time traffic. Herein, we propose a method, called Reduced Buffering Scheme, to conduct the traffic through multiple HaRTES switches in a multi-hop HaRTES architecture. In order to enable the new scheduling method we propose to modify the HaRTES switch structure. Moreover, we develop a response time analysis for the new method. We also compare the proposed method with a method previously proposed, called Distributed Global Scheduling, based on their traffic response times. We show that, the new method forwards all types of traffic including the highest, the medium and the lowest priority, faster than the previous method in most of the cases. Furthermore, we show that the new method performs even better for larger networks compared with the previous one.

关键词： Delays Job shop scheduling Ports (Computers) Protocols real-time systems Switches time factors Switches Job shop scheduling real-time systems time Factors Spread spectrum communication protocols switched Ethernet Traffic Buffer solutions Ethernet networks delay single turnout Types of traffic time series analysis

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Learning Based Power Management for Periodic real-time Tasks 16

Learning Based Power Management for Periodic Real-Time Tasks

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16th ieee Int Conf on High Performance computing and Communications/11th ieee Int Conf on embedded Software and systems\6th Int Symposium on Cyberspace Safety and Security

作者： ul Islam, Fakhruddin Muhammad Mahbub Lin, Man St Francis Xavier Univ Dept Math Stat & Comp Sci Antigonish NS Canada

ISBN: (纸本)9781479961238

With the extensive use of portable battery powered devices in the new computing era, the power consumption problem of embedded devices has received a lot of attention in order to gain long battery life for enormous prospective. In modern processors, dynamic voltage and frequency scaling (DVFS) has been commonly used for energy reduction and temperature control. But with the variety of processor configurations, a DVFS arrangement that is energy efficient for one processor might not be appropriate for others. Furthermore, the efficiency of DVFS is also affected by the CPU intensiveness of the underlying tasks of the applications. In this paper, we propose a novel reinforcement learning based algorithm that dynamically controls the voltage and frequency of real-time systems and adjusts itself with diverse environments for optimal use of energy. Experimental results show that our proposed method can save significant amount of energy compared to other approaches.

关键词： real-time systems reinforcement learning DVFS task characterization

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Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR)

Efficient QR Decomposition Using Low Complexity Column-wise ...

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27th international conference on VLSI Design / 13th international conference on embedded systems (VLSID)

作者： Merchant, Farhad Chattopadhyay, Anupam Garga, Ganesh Nandy, S. K. Narayan, Ranjani Gopalan, Nandhini Indian Inst Sci CADLab Bangalore 560012 Karnataka India Rhein Westfal TH Aachen UMIC Res Ctr MPSoC Architectures D-52074 Aachen Germany Morphing Machines Pvt Ltd Malleshwara Karnataka India

ISBN: (纸本)9781479925124

QR decomposition (QRD) is a widely used Numerical Linear Algebra (NLA) kernel with applications ranging from SONAR beamforming to wireless MIMO receivers. In this paper, we propose a novel Givens Rotation (GR) based QRD (GR QRD) where we reduce the computational complexity of GR and exploit higher degree of parallelism. this low complexity Column-wise GR (CGR) can annihilate multiple elements of a column of a matrix simultaneously. the algorithm is first realized on a Two-Dimensional (2 D) systolic array and then implemented on REDEFINE which is a Coarse Grained run-time Reconfigurable Architecture (CGRA). We benchmark the proposed implementation against state-of-the-art implementations to report better throughput, convergence and scalability.

关键词： QR Decomposition Systolic Arrays CGRA

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An Evaluation of Code Generation of Dataflow Languages on Manycore Architectures 20

An Evaluation of Code Generation of Dataflow Languages on Ma...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Savas, Suleyman Gebrewahid, Essayas Ul-Abdin, Zain Nordstrom, Tomas Yang, Mingkun Halmstad Univ Ctr Res Embedded Syst Halmstad Sweden

ISBN: (纸本)9781479939541

Today computer architectures are shifting from single core to manycores due to several reasons such as performance demands, power and heat limitations. However, shifting to manycores results in additional complexities, especially with regard to efficient development of applications. Hence there is a need to raise the abstraction level of development techniques for the manycores while exposing the inherent parallelism in the applications. One promising class of programming languages is dataflow languages and in this paper we evaluate and optimize the code generation for one such language, CAL. We have also developed a communication library to support the intercore communication. the code generation can target multiple architectures, but the results presented in this paper is focused on Adapteva's many core architecture Epiphany. We use the twodimensional inverse discrete cosine transform (2D-IDCT) as our benchmark and compare our code generation from CAL with a hand-written implementation developed in C. Several optimizations in the code generation as well as in the communication library are described, and we have observed that the most critical optimization is reducing the number of external memory accesses. Combining all optimizations we have been able to reduce the difference in execution time between auto-generated and handwritten implementations from a factor of 4.3x down to a factor of only 1.3x.

关键词： Manycore Dataflow Languages code generation Actor Machine 2D-IDCT Epiphany evaluation

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A Context Aware Cache Controller to Bridge the Gap Between theory and Practice in real-time systems 20

A Context Aware Cache Controller to Bridge the Gap Between T...

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20th ieee international conference on embedded and real- time computing systems and applications (RTCSA 2014).

作者： Allard, Yannick Nelissen, Geoffrey Goossens, Joel Milojevic, Dragomir Univ Libre Bruxelles PARTS Res Ctr Brussels Belgium Polytech Inst Porto ISEP CISTER INESC TEC Oporto Portugal

ISBN: (纸本)9781479939541

Nowadays, most processing platforms make use of cache memories to improve the execution speed of the tasks running on the processors. However, when a processor switches from a task to another, the caches must be reloaded with the context of the upcoming task. this is time consuming and is usually not predictable and thus affects the worst-case execution time of the task. Such unpredictability should be avoided in realtime systems in which the instant at which a result is available is as important as the result itself. In this paper, we present a hardware component named hardware context switch (HwCS) which replaces the standard L1 cache controller of a processor. It divides the cache in two interchangeable layers and enables to save or restore the content of one layer while the second is simultaneously used as a usual cache by the processor. Saving the cache content after a preemption and restoring this content before resuming the execution of the preempted task, makes the preemption overheads negligible in comparison to the task worst-case execution times. It is theoretically proven that the existing scheduling theory can be used "as is" with the HwCS by simply reducing the task deadlines, thereby bridging the gap between theory and practice. the HwCS has been implemented in an uniprocessor system as a proof of concept. the first results show a neat improvements on the processor utilisation for a small cost in silicon surface.

关键词： Program processors Switches Cache memory Program processors Switches real-time systems PROCESSOR uniprocessor system execution speed execution time one layer

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