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Deadline-aware load balancing for MapReduce

Deadline-aware load balancing for MapReduce

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Zhao-Rong Lai Che-Wei Chang Xue Liu Tei-Wei Kuo Pi-Cheng Hsiu Academia Sinica Research Center for Information Technology Innovation Taiwan Department of Computer Science and Information Engineering National Taiwan University Taiwan Department of Computer Science and Information Engineering Chang Gung University Taiwan School of Computer Science McGill University Montreal Canada Graduate Institute of Networking and Multimedia National Taiwan University Taiwan

ISBN: (纸本)9781479939541

As cloud computing gains its momentum in big data processing and providing on-line services, there are increasing demands to offer responsive services to users and to improve the effectiveness in server utilization. Most previous work studied the fairness among user requests, the workload balancing among servers, and the support of real-time applications individually. Different from those state-of-the-art work, we focus on the joint considerations of workload balancing and deadline satisfaction in facing user requests for MapReduce. In particular, scheduling algorithms are proposed with a constant approximation bound to balance the server workloads and, at the same time to meet the response time requirements of MapReduce jobs. the proposed scheduling algorithms are then implemented with our proposed resource manager for the open source implementation of Hadoop. We evaluate our design based on performance metrics including balancing server workloads and meeting jobs' response-time requirements. Experimental results show the effectiveness of our design through real testbed implementation.

关键词： Schedules Equations Clustering algorithms Scheduling algorithms Cloud computing real-time systems Approximation algorithms

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Energy-efficient allocation of real-time applications onto Heterogeneous Processors

Energy-efficient allocation of real-time applications onto H...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Alexei Colin Arvind Kandhalu Ragunathan Rajkumar Dept. of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA

Self-powered vehicles that interact with the physical world, such as spacecraft, require computing platforms with predictable timing behavior and a low energy demand. Energy consumption can be reduced by choosing energy-efficient designs for both hardware and software components of the platform. We leverage the state-of-the-art in energy-efficient hardware design by adopting Heterogeneous Multi-core Processors with support for Dynamic Voltage and Frequency Scaling and Dynamic Power Management. We address the problem of allocating real-time software components onto heterogeneous cores such that total energy is minimized. Our approach is to start from an analytically justified target load distribution and find a task assignment heuristic that approximates it. Our analysis shows that neither balancing the load nor assigning all load to the “cheapest” core is the best load distribution strategy, unless the cores are extremely alike or extremely different. the optimal load distribution is then formulated as a solution to a convex optimization problem. A heuristic that approximates this load distribution and an alternative method that leverages the solution explicitly are proposed as viable task assignment methods. the proposed methods are compared to state-of-the-art on simulated problem instances and in a case study of a soft-real-time application on an off-the-shelf ARM *** heterogeneous processor.

关键词： Energy efficiency

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Design and implementation of a multi-node wifi heart rate variability analysis system

Design and implementation of a multi-node wifi heart rate va...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Kai Li Xin Wang Jianhua Shen Dept. of Computer Science and Technology East China Normal Unisersity Shanghai P. R. China

ISBN: (纸本)9781479939541

this paper has designed a kind of WIFI multi-node heart rate variability (HRV) analysis system, consisting of several ElectroCardioGram (ECG) acquisition nodes and an analysis platform based on ARM Cortex-A8 processor. the node oversamples ECG signal through a photoelectric ear clip and filters it with FIR window before sending it to the platform with specific format package by WIFI module. the platform extracts ECG signal of each node from the received packages in real time and RR intervals are acquired from ECG signal by differential threshold algorithm so as to calculate time domain parameters. Before performing frequency domain analysis on RR intervals, the baseline wander is removed from RR intervals by db6 wavelet and RR intervals is resampled by cubic spline interpolation. All algorithm for each node can be done in short period by means of multi-thread and NEON technique. the system is promising for multi-node with real-time and stable operation and accurate analysis result, which can be widely used in medical care, the collective movement training and psychological testing.

关键词： Electrocardiography Heart rate variability Frequency-domain analysis ieee 802.11 Standards real-time systems Wavelet analysis Optimization

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CCM: Low cost dynamic data exchange to emulate RAM on NAND flash

CCM: Low cost dynamic data exchange to emulate RAM on NAND f...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Junhua Zhao Hejun Wu Yongjian Zhao Weiwei Liu Department of Computer Science Sun Yat-sen University Guangzhou China

ISBN: (纸本)9781479939541

In embedded systems, it brings great benefits to use NAND flash for dynamic data exchange like using RAM, since RAM is usually expensive and consumes much energy. However, the major hardware limitations of NAND flash make it difficult to directly and dynamically read\write\erase on NAND flash. Traditional virtual memory systems are all based on flash translation layer and file system, which lead to frequently flash read\write\erase and more RAM requirement. To address this problem, we propose a Comet Circle Model (CCM) to emulate RAM for low cost embedded systems in this paper. CCM dynamically makes the distribution of valid pages in NAND flash follow a fixed function through integrating its physical page-level mapping and circularly write-back techniques. As a result, CCM can select a block without valid pages to write data almost every time in data writing, which avoids data moving among blocks. Both theoretical analysis and experimental results show that the data moving times and erase counts of CCM closely reach the theoretical lower bounds.

关键词： Flash memories Random access memory Indexes File systems Writing embedded systems Standards

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Optimal and fast composition of resource-sharing components in hierarchical real-time systems

Optimal and fast composition of resource-sharing components ...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： M.M.H.P. van den Heuvel M. Behnam R.J. Bril J.J. Lukkien T. Nolte Technische Universiteit Eindhoven Eindhoven AZ The Netherlands Mälardalen Real-Time Research Centre (MRTC) Västerås Sweden

In this paper we consider various flavors of the stack resource policy (SRP) for arbitrating access to shared resources in a hierarchical scheduling framework (HSF) upon a uni-processor. We propose algorithms for exploring and selecting the (local) resource ceilings within components, such that it results in an optimal composition of resource-sharing components in an HSF. Existing methods are non-optimal, because (i) they optimize just the length of global non-preemptive execution of tasks and (ii) they do not detect whether or not resources are shared globally (i.e., between tasks of different components). Lifting these limitations leads to an exponential growth of the design space. this paper contributes a fast three-step methodology which lifts these limitations, i.e., we apply the SRP at each level of the HSF to just the resources being shared. Our algorithm selects those component interfaces (i.e., by fixing the local resource ceilings of each component) that minimize the system load.

关键词： Protocols Processor scheduling Synchronization Resource management real-time systems Algorithm design and analysis

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A hardware-software co-design experiments platform for NAND flash based on Zynq

A hardware-software co-design experiments platform for NAND ...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Debao Wei Youhua Gong Liyan Qiao Libao Deng School of Electrical Engineering and Automation Harbin Institute of Technology Harbin China School of Information and Electrical Engineering Harbin Institute of Technology at Weihai Weihai China

ISBN: (纸本)9781479939541

In this paper we describe a hardware-software co-design experiments platform for NAND flash based on Zynq. Our novel experimental platform utilizes the PL (Programmable Logic within Zynq) to achieve the timing control and bad block management of NAND flash, and to provide a high-speed parallel algorithm verification environment for users. Besides, it utilizes the PS (Processing System within the Zynq) to achieve the famous hybrid FAST FTL algorithm, so it can also provide a valuation baseline of FTL algorithms, and provide the running environment for compute-intensive data processing algorithms, like compression or error correction. Test results show that our experiment platform has a high speed and stable performance to manage the storage data, and can effectively evaluate the indicators of storage system based on NAND flash.

关键词： Flash memories Instruction sets Algorithm design and analysis Universal Serial Bus Data communication Hardware File systems

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A management architecture of cloud server systems

A management architecture of cloud server systems

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Hua Nie Gongbo Li Xingkui Liu Xiaojun Yang Keping Long School of Computer and Communication Engineering University of Science and Technology Beijing Beijing P. R. China University of Chinese Academy of Sciences Beijing P. R. China Institute of Computing Technology Chinese Academy of Sciences Beijing P. R. China Dawning Information Industry Co. Ltd. Beijing P. R. China

ISBN: (纸本)9781479939541

With the development of the cloud computing, the servers we use today are not suitable for data centers very well because of high power consumption and low density. In this paper, we propose a cloud server of low power consumption, high density and good scalability. We employ a reconfigurable architecture to build the cloud server and we can change or update the architecture of the cloud server from remote easily. Furthermore, we build a LAN upon a 2D torus interconnection network using distributed DHCP servers and distributed ARP proxies cooperated with an integrated switch. the experimental result of the prototype shows the availability and high throughput of the network in the cloud server system.

关键词： Servers Field programmable gate arrays IP networks System-on-chip Multiprocessor interconnection Switches

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Reduced buffering solution for multi-hop HaRTES switched Ethernet networks

Reduced buffering solution for multi-hop HaRTES switched Eth...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Mohammad Ashjaei Moris Behnam Paulo Pedreiras Reinder J. Bril Luis Almeida thomas Nolte MRTC/Mälardalen University Västerås Sweden DETI/IT/University of Aveiro Aveiro Portugal Technische Universiteit Eindhoven (TU/e) The Netherlands IT/DEEC/University of Porto Portugal

In the context of switched Ethernet networks, multi-hop communication is essential as the networks in industrial applications comprise a high amount of nodes, that is far beyond the capability of a single switch. In this paper, we focus on multi-hop communication using HaRTES switches. the HaRTES switch is a modified Ethernet switch that provides real-time traffic scheduling, dynamic Quality-of-Service and temporal isolation between real-time and non-real-time traffic. Herein, we propose a method, called Reduced Buffering Scheme, to conduct the traffic through multiple HaRTES switches in a multi-hop HaRTES architecture. In order to enable the new scheduling method we propose to modify the HaRTES switch structure. Moreover, we develop a response time analysis for the new method. We also compare the proposed method with a method previously proposed, called Distributed Global Scheduling, based on their traffic response times. We show that, the new method forwards all types of traffic including the highest, the medium and the lowest priority, faster than the previous method in most of the cases. Furthermore, we show that the new method performs even better for larger networks compared with the previous one.

关键词： Switches time factors Delays real-time systems Ports (Computers) Protocols Job shop scheduling

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Multi-objective aware design flow for coarse-grained systems on chip

Multi-objective aware design flow for coarse-grained systems...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Peng Chen Chao Wang Xi Li Xuehai Zhou Department of Computer Science University of Science and Technology of China Hefei Anhui China

this paper presents a software and hardware co-design flow for the coarse-grained systems on chip. It enables a multi-target design space exploration (MT-DSE) algorithm with multiple objectives such as chip area utilization, energy consumption, core efficiency, interconnection structure, application workload and speedup aware. With the help of the MT-DSE tool, the proposed design flow can supply a valuable assistance for architecture designers to develop a well trade-off multi-processor system. In contrast, most of state-of-the-art design space exploration tools rely on varieties of simulations or implementations that are quite time-consuming. Benefit from no such dependences, the MT-DSE method could turn out the optimized alternative very fast with multiple factors balanced. Besides, the tool is employed at a very early stage in the component based systems design and only needs a little profiling information which can greatly reduce the development term of the design. As an illustration, the JPEG compression algorithm is chosen to demonstrate how the tool exploits a given application and guides to build the most desired architecture.

关键词： Computer architecture Hardware Space exploration Program processors Algorithm design and analysis Transform coding

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Component-based analysis of hierarchical scheduling using linear hybrid automata

Component-based analysis of hierarchical scheduling using li...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Youcheng Sun Giuseppe Lipari Romain Soulat Laurent Fribourg Nicolas Markey Scuola Superiore Sant’ Anna LSV CNRS

Formal methods (e.g. timed Automata or Linear Hybrid Automata) can be used to analyse a real-time system by performing a reachability analysis on the model. the advantage of using formal methods is that they are more expressive than classical analytic models used in schedulability analysis. For example, it is possible to express state-dependent behaviour, arbitrary activation patterns, etc. In this paper we use the formalism of Linear Hybrid Automata to encode a hierarchical scheduling system. In particular, we model a dynamic server algorithm and the tasks contained within, abstracting away the rest of the system, thus enabling component-based scheduling analysis. We prove the correctness of the model and the decidability of the reachability analysis for the case of periodic tasks. then, we compare the results of our model against classical schedulability analysis techniques, showing that our analysis performs better than analytic methods in terms of resource utilisation. We further present two case studies: a component with state-dependent tasks, and a simplified model of a real avionics system. Finally, through extensive tests with various configurations, we demonstrate that this approach is usable for medium-size components.

关键词： Servers Automata Analytical models Heuristic algorithms Processor scheduling Partitioning algorithms real-time systems

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