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Energy efficient routing techniques with guaranteed reliability based on multi-level uncertain graph

Energy efficient routing techniques with guaranteed reliabil...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Wendi Nie Yaoxin Duan Kaijie Wu Qingfeng Zhuge Edwin H.M. Sha College of Computer Science Chongqing University Chongqing China Key Laboratory of Dependable Service Computing in Cyber Physical Society Ministry of Education Chongqing China Department of Computer Science University of Texas at Dallas Richardson TX USA

In recent years, an emerging low-power system “wireless sensor networks (WSNs)” attracts significant research interests. the energy of the distributed sensors is an essential constraint in such a complex distributed embedded system. Routing techniques in WSNs always follow a high-performance and energy-efficient way. However, conventional routing schemes of WSNs generally do not take the timing and reliability requirements into account when making routing decisions to prolong the lifetime of WSNs. Moreover, due to environmental factors such as temperature, humidity and signal interference, the bandwidths of links in a WSN various from time to time like random variables, which demands special considerations when timing and reliability requirements are presented for routing. In this paper, we introduce a graph model called Multi-level Uncertain Graph (MUG) to deal with the situation. Based on the MUG model, we define the new problem as the Energy-Balanced Transmission (EBT) Problem, and propose a EBT-Solver to maximize the lifetime of the WSN subject to timing and reliability constraints. Experimental results show that EBT-Solver solves EBT problem to the best advantage of energy balance and network's lifetime.

关键词： Wireless sensor networks Reliability Timing Routing real-time systems Bandwidth Probability distribution

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Federated scheduling for stochastic parallel real-time tasks

Federated scheduling for stochastic parallel real-time tasks

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Jing Li Kunal Agrawal Christopher Gill Chenyang Lu Department of Computer Science and Engineering Washington University in St. Louis

Federated scheduling is a strategy to schedule parallel real-time tasks: It allocates a dedicated cluster of cores to each high-utilization task (utilization ≥ 1); It uses a multiprocessor scheduling algorithm to schedule and execute all low-utilization tasks sequentially, on a shared cluster of the remaining cores. Prior work has shown that federated scheduling has the best known capacity augmentation bound of 2 for parallel tasks with implicit deadlines. In this paper, we explore the soft real-time performance of federated scheduling and address average-case workloads instead of worst-case ones. In particular, we consider stochastic tasks - tasks for which execution time and critical-path length are random variables. In this case, we use bounded expected tardiness as the schedulability criterion. We define a stochastic capacity augmentation bound and prove that federated scheduling algorithms guarantee the same bound of 2 for stochastic tasks. We present three federated mapping algorithms with different complexities for core allocation. All of them guarantee bounded expected tardiness and provide the same capacity augmentation bound. In practice, however, we expect them to provide different performance, both in terms of the task sets they can schedule and the actual tardiness they guarantee. therefore, we present numerical evaluations using randomly generated task sets to examine the practical differences between the three algorithms.

关键词： real-time systems Stochastic processes Processor scheduling Resource management Scheduling Schedules Random variables

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A context aware cache controller to bridge the gap between theory and practice in real-time systems

A context aware cache controller to bridge the gap between t...

引用

ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Yannick Allard Geoffrey Nelissen Joël Goossens Dragomir Milojevic PARTS Research Centre Université libre de Bruxelles (ULB) CISTERIINESC-TEC ISEP Polytechnic Institute of Porto

Nowadays, most processing platforms make use of cache memories to improve the execution speed of the tasks running on the processors. However, when a processor switches from a task to another, the caches must be reloaded with the context of the upcoming task. this is time consuming and is usually not predictable and thus affects the worst-case execution time of the task. Such unpredictability should be avoided in real-time systems in which the instant at which a result is available is as important as the result itself. In this paper, we present a hardware component named hardware context switch (HwCS) which replaces the standard L1 cache controller of a processor. It divides the cache in two interchangeable layers and enables to save or restore the content of one layer while the second is simultaneously used as a usual cache by the processor. Saving the cache content after a preemption and restoring this content before resuming the execution of the preempted task, makes the preemption overheads negligible in comparison to the task worst-case execution times. It is theoretically proven that the existing scheduling theory can be used “as is” with the HwCS by simply reducing the task deadlines, thereby bridging the gap between theory and practice. the HwCS has been implemented in an uniprocessor system as a proof of concept. the first results show a neat improvements on the processor utilisation for a small cost in silicon surface.

关键词： Program processors Switches

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An implementation of partitioned scheduling scheme for hard real-time tasks in multicore Linux with fair share for Linux tasks

An implementation of partitioned scheduling scheme for hard ...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： N. Saranya R. C. Hansdah Dept of Computer Science and Automation Indian Institute of Science Bangalore India

the correctness of a hard real-time system depends upon its ability to meet all its deadlines. Existing real-time systems use either a pure real-time scheduler or a real-time scheduler embedded as a real-time scheduling class in the scheduler of an operating system (OS). Existing implementations of schedulers in multicore systems that support real-time and non-real-time tasks, permit the execution of non-real-time tasks in all the cores with priorities lower than those of real-time tasks, but interrupts and softirqs associated with these non-real-time tasks can execute in any core with priorities higher than those of real-time tasks. As a result, the execution overhead of real-time tasks is quite large in these systems, which, in turn, affects their runtime. In order that the hard real-time tasks can be executed in such systems with minimal interference from other Linux tasks, we propose, in this paper, an integrated scheduler architecture, called SchedISA, which aims to considerably reduce the execution overhead of real-time tasks in these systems. In order to test the efficacy of the proposed scheduler, we implemented partitioned earliest deadline first (P-EDF) scheduling algorithm in SchedISA on Linux kernel, version 3.8, and conducted experiments on Intel core i7 processor with eight logical cores. We compared the execution overhead of real-time tasks in the above implementation of SchedISA with that in SCHED_DEADLINE's P-EDF implementation, which concurrently executes real-time and non-real-time tasks in Linux OS in all the cores. the experimental results show that the execution overhead of real-time tasks in the above implementation of SchedISA is considerably less than that in SCHED_DEADLINE. We believe that, with further refinement of SchedISA, the execution overhead of real-time tasks in SchedISA can be reduced to a predictable maximum, making it suitable for scheduling hard real-time tasks without affecting the CPU share of Linux tasks.

关键词： real-time systems Linux Multicore processing Kernel Scheduling algorithms Hardware

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Keynote: “Non-volatile memory innovation”

Keynote: “Non-volatile memory innovation”

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Tei-Wei Kuo National Taiwan University Taipei TW

Summary form only given. As flash memory gains its huge momentum in the storage market, people have high expectation on other potential roles that could be played by non-volatile memory. It has been a grand challenge to position selected non-volatile memory technologies in the memory hierAs flash memory gains its huge momentum in the storage market, people have high expectation on other potential roles that could be played by non-volatile memory. It has been a grand challenge to position selected non-volatile memory technologies in the memory hierarchy. In this talk, I will take flash memory and phased change memory (PCM) as examples to address the challenges and design methodologies for non-volatile memory as a storage medium or to serve as the role of DRAM. the talk will be concluded by moving the discussion forward to the opportunities of non-volatile memory in system designs, such as server cache and data storage in data ***. In this talk, I will take flash memory and phased change memory (PCM) as examples to address the challenges and design methodologies for non-volatile memory as a storage medium or to serve as the role of DRAM. the talk will be concluded by moving the discussion forward to the opportunities of non-volatile memory in system designs, such as server cache and data storage in data manipulation.

关键词： Nonvolatile memory Educational institutions real-time systems Awards activities Ash Computer science conferences

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An evaluation of code generation of dataflow languages on manycore architectures

An evaluation of code generation of dataflow languages on ma...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Süleyman Savas Essayas Gebrewahid Zain Ul-Abdin Tomas Nordström Mingkun Yang Centre for Research on Embedded Systems Halmstad University Halmstad Sweden

Today computer architectures are shifting from single core to manycores due to several reasons such as performance demands, power and heat limitations. However, shifting to manycores results in additional complexities, especially with regard to efficient development of applications. Hence there is a need to raise the abstraction level of development techniques for the manycores while exposing the inherent parallelism in the applications. One promising class of programming languages is dataflow languages and in this paper we evaluate and optimize the code generation for one such language, CAL. We have also developed a communication library to support the intercore communication. the code generation can target multiple architectures, but the results presented in this paper is focused on Adapteva's many core architecture Epiphany. We use the two-dimensional inverse discrete cosine transform (2D-IDCT) as our benchmark and compare our code generation from CAL with a hand-written implementation developed in C. Several optimizations in the code generation as well as in the communication library are described, and we have observed that the most critical optimization is reducing the number of external memory accesses. Combining all optimizations we have been able to reduce the difference in execution time between auto-generated and handwritten implementations from a factor of 4.3× down to a factor of only 1.3×.

关键词： Multicore processing Ports (Computers) Program processors Libraries Generators Programming

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Non-volatile registers aware instruction selection for embedded systems

Non-volatile registers aware instruction selection for embed...

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Mimi Xie Chen Pan Jingtong Hu Chun Jason Xue Qingfeng Zhuge School of Electrical and Computer Engineering Oklahoma State University Stillwater OK USA Department of Computer Science City University of Hong Kong Kowloon Hong Kong College of Computer Science Chongqing University Chongqing China

ISBN: (纸本)9781479939541

It is common that embedded systems are powered by limited and unstable power supply. In order to improve the reliability of embedded systems against unstable power supply, non-volatile memory (e.g. FRAM) based registers are proposed for embedded processors. FRAM-based registers have many advantages over traditional CMOS-based volatile registers such as non-volatility and power-economy. However, similar to other non-volatile memories (NVM), write operations to FRAM consume more time and power compared with read operations and limit the lifetime of the registers. Existing compiler optimization techniques never take the writes to registers into consideration. therefore, code generated by a traditional compiler has an adverse effect on processors with non-volatile registers. this paper aims at improving the lifetime and efficiency of non-volatile registers based embedded processors by generating NV register friendly code. To achieve the goal, in this paper, we investigate the usage of memory access instructions and propose the NV Register Aware Instruction Selection (NAIS) algorithm to reduce the write operations on non-volatile registers. According to the experimental results, the proposed algorithm can reduce the writes on NV registers by 66.89% on average when compared with GCC [1]. thus the lifetime of NV registers is extended to 2 times as long as before on average. the time cost is reduced by 56.68% and the energy consumption is reduced by 59.76% on average.

关键词： Registers Nonvolatile memory Labeling Random access memory Program processors Ferroelectric films Nickel

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Service guarantee exploration for mixed-criticality systems

Service guarantee exploration for mixed-criticality systems

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ieee international conference on embedded and real-time computing systems and applications (RTCSA)

作者： Hang Su Nan Guan Dakai Zhu University of Texas at San Antonio USA Northeastern University China Uppsala University Sweden

Most mixed-criticality scheduling algorithms have the problem of service interruption for low-critical tasks, which has prompted several recent studies on providing various service guarantees for such tasks. In this paper, focusing on dual-criticality systems, we explore the best achievable service guarantees for low-critical tasks in different running modes and investigate their trade-offs. Specifically, the Elastic Mixed-Criticality (E-MC) task model is first extended to allow each low-critical task to have a pair of small and large periods, which represent its service guarantees in the low and high running modes, respectively. To improve system schedulability under a mode-switch EDF scheduler, virtual deadlines for high-critical tasks are also incorporated. then, we develop new demand bound functions (DBFs) following a unified approach and analyze the corresponding schedulability conditions. the service guarantees for low-critical tasks are explored via the adjustment of their paired periods. We show that, compared to the state-of-the-art solution, the proposed schedulability test derived from the refined DBFs can accommodate smaller periods and thus achieve better service guarantees for low-critical tasks. Moreover, there are some interesting trade-offs between the service guarantees and a few guidelines are attained for properly specifying them.

关键词： Atmospheric modeling Adaptation models

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Control Mechanism to Solve False Blocking Problem at MAC Layer in Wireless Sensor Networks

Control Mechanism to Solve False Blocking Problem at MAC Lay...

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international conference on VLSI Design

作者： Brajendra K. Singh Kemal E. Tepe Mohammed A.S. Khalid Department of Electrical and Computer Engineering University of Windsor Windsor Canada

Contention based MAC protocols for wireless sensor networks (WSNs) suffer from the problem of false blocking of channel access due to unsuccessful attempts of RTS transmission by their neighboring nodes. this does not only reduce the network throughput, but also results in inconsistent and unpredictable data packet transmission pattern, which is unacceptable for real-time applications. A control mechanism that solves the false blocking problem is designed and introduced in this paper. In this approach, an additional control signal, called clear channel (CC), is used to facilitate the medium access decision. the proposed solution works for single-stream as well as multi-stream communication scenarios. Simulation results show that the solution helps the network to provide consistent and predictable delay performance while maintaining similar network throughput and energy consumption as compared to other general purpose MAC protocols for WSNs. With this solution, wireless sensors can be used in real-time sensor data communication.

关键词： Very large scale integration embedded systems

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Efficient Online Benefit-Aware Multiprocessor Scheduling Using an Online Choice of Approximation Algorithms

Efficient Online Benefit-Aware Multiprocessor Scheduling Usi...

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ieee international conference on High Performance computing and Communications (HPCC)

作者： Behnaz Sanati Albert M.K. Cheng Computer Science Department University of Houston TX USA

Maximizing the benefit gained by soft real-time jobs in many applications and embedded systems is highly needed to provide an acceptable QoS (Quality of Service). this paper considers a benefit model for on-line pre-emptive multiprocessor scheduling. the goal is to maximize the total benefit gained by the jobs that meet their deadlines. this method prioritizes the jobs using their benefit density functions and schedules them in a real-time basis. We propose an online choice of two approximation algorithms in order to partition the jobs among identical processors at the time of their arrival without using any statistics. Our analysis and experiments show that we are able to maximize the gained benefit and decrease the computational complexity (compared to existing algorithms) while minimizing make span (response time, also referred to as cost), with fewer missed deadlines and more balanced usage of processors. Our solution is applicable to a wide variety of soft real-time applications and embedded systems such as, but not limited to multimedia applications, medical monitoring systems or those with higher utilization such as bursty hosting servers.

关键词： Program processors Approximation algorithms Algorithm design and analysis Processor scheduling Approximation methods real-time systems Partitioning algorithms

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