the tight coupling among computation, sensing and control found in Cyber-Physical systems (CPS) often requires information processing to be completed within strict timing deadlines. Traditional hard real-time scheduli...
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ISBN:
(纸本)9781479908516
the tight coupling among computation, sensing and control found in Cyber-Physical systems (CPS) often requires information processing to be completed within strict timing deadlines. Traditional hard real-time scheduling algorithms require the use of the worst-case execution times to guarantee that deadlines will be met. Unfortunately, many algorithms with parameters derived from sensing the physical world suffer from large variations in execution time, which leads to pessimistic overall utilization. For example, object tracking in a computer vision system is highly dependent on the number and size of the objects within the camera's field of view. In this paper, we present the formal description of ZS-QRAM [8], a scheduling approach that allows system designers to flexibly assign execution times and application-derived utility to tasks in order to maximize total system utility even in the presence of highly variable processing estimates. In particular, we provide a detailed description of the algorithm, the formal proofs for its temporal protection and a detail evaluation. Our evaluation uses the Utility Degradation Resilience (UDR) metric presented in [8]. Our results show that ZS-QRAM is able to obtain four times as much UDR as ZSRM, a previous overbooking approach, and almost twice as much UDR as Rate-Monotonic with Period Transformation (RM/TP) even when the latter does not provide temporal protection.
the proceedings contain 68 papers. the topics discussed include: reducing preemptions and migrations in real-time multiprocessor scheduling algorithms by releasing the fairness;mode transition for online scheduling of...
ISBN:
(纸本)9780769545028
the proceedings contain 68 papers. the topics discussed include: reducing preemptions and migrations in real-time multiprocessor scheduling algorithms by releasing the fairness;mode transition for online scheduling of adaptive real-timesystems on multiprocessors;utilization-controlled task consolidation for power optimization in multi-core real-timesystems;a reliability enhancement mechanism for high-assurance MLC flash-based storage systems;limiting worst-case end-to-end latency when traffic increases in a switched avionics network;design and implementation of on-chip adaptive router with predictor for regional congestion;HW resource componentizing for addressing the mega-complexity of cyber-physical systems;Virtual Lock: a smartphone application for personal surveillance using camera sensor networks;dynamic activation timing configuration for product line development;and stabilization of projected image for wearable walking support system using Pico-projector.
the implementation of low-cost 3D Stereo Vision systems requires stereo matching algorithms. Various efforts have been reported in the literature, however, these systems require substantial hardware resources. the con...
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ISBN:
(纸本)9781479931637
the implementation of low-cost 3D Stereo Vision systems requires stereo matching algorithms. Various efforts have been reported in the literature, however, these systems require substantial hardware resources. the contribution of the present work is on a low-cost real-time system, which was fully implemented on a small Xilinx FPGA. the system presented in this work extends previous results of the authors through design space exploration, architecture improvements and careful problem sizing
the EC project parMERASA investigates techniques for the parallelization of industrial real-timeapplications from automotive, avionic, and construction machinery domains. the aim is to execute such applications on ma...
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ISBN:
(纸本)9780769550886
the EC project parMERASA investigates techniques for the parallelization of industrial real-timeapplications from automotive, avionic, and construction machinery domains. the aim is to execute such applications on many-core processors with up to 64 cores. the system software plays a key role in the deployment of applications. However, requirements of application domains differ widely, and thus no general solution can be implemented. In this paper we present the cross-domain system architecture utilized in the parMERASA project to provide Runtime Environments (RTEs) for the three different domains. the approach eases the implementation of domain-specific RTEs through a generic kernel library that provides basic hardware abstractions and timing-analyzable synchronization mechanisms.
In order to predicate the schedulability of real-timeembedded system in the model design stage, a new schedulability analysis method for embedded system models using Architecture Analysis and Design Language (AADL) i...
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ISBN:
(纸本)9780769550398
In order to predicate the schedulability of real-timeembedded system in the model design stage, a new schedulability analysis method for embedded system models using Architecture Analysis and Design Language (AADL) is presented in this paper. through analyzing system architecture, component properties and component connections, we build the Resource Competition Model (RCM) for the AADL model. Based on the RCM, the respond time of thread components can be calculated, and we get the schedulability of system AADL model. this approach is on the model level to analyze the schedulability of systems without code implement. It has higher calculation efficiency, and a lower requirement for the system description. At last, a case-study is carried out to show the schedulability analysis process for an AADL model.
In this paper, we propose a very accurate energy model for streaming applications modeled as Polyhedral Process Networks (PPN) and mapped onto tile-based MPSoC platforms with distributed memory. the energy model is ba...
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ISBN:
(纸本)9781479901036
In this paper, we propose a very accurate energy model for streaming applications modeled as Polyhedral Process Networks (PPN) and mapped onto tile-based MPSoC platforms with distributed memory. the energy model is based on the well-defined properties of the PPN application model. To guarantee the accuracy of the energy model, values of important model parameters are obtained by real measurements. the proposed energy model is applicable to different types of processors and communication infrastructures within an MPSoC platform. the energy model is evaluated on FPGA-based MPSoC platforms against real measurements of energy consumption from the FPGA. the obtained energy estimates are highly accurate with an average error of 4% and a standard deviation of 3%. the average model evaluation time per design point takes 2.5 minutes for considered cases, which is very good given the high accuracy of the model.
In this paper, we study run-time reconfiguration problem for tolerating core failures on NoC manycore platforms with following three objectives: (1) maintaining the maximal timing similarity between real-timeembedded...
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ISBN:
(纸本)9780769550886
In this paper, we study run-time reconfiguration problem for tolerating core failures on NoC manycore platforms with following three objectives: (1) maintaining the maximal timing similarity between real-timeembedded application' timing properties before and after the system reconfiguration;(2) guaranteeing to meet real-timeembedded application's deadline requirements after system reconfiguration;and (3) minimizing the task migration time delay. Two approaches, i.e. mixed integer quadratic programming (MIQP) based approach and a heuristic largest influence core first (LICF) approach, are developed to derive a reconfiguration strategy that meets the three objectives. the MIQP approach is able to obtain the optimal solution and can be used at run-time if extra memory is available. For memory limited systems, the LICF approach can be used to obtain a solution in polynomial timethat is near optimal.
Modern embeddedsystems require both high performance computing capability and low power/energy consumption in order to meet ever increasing customer demands. Recently, several semiconductor manufacturers have provide...
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ISBN:
(纸本)9780769550886
Modern embeddedsystems require both high performance computing capability and low power/energy consumption in order to meet ever increasing customer demands. Recently, several semiconductor manufacturers have provided a new hybrid multiprocessing model which couples an FPGA with programmable processors. this constellation of processing elements in SoC platforms certainly provides needed performance while still keeping flexibility. However, several questions are yet to be answered to understand and use the platform better: What will the development flow look like to handle both software programmable processors and hardware blocks? What are the key points to map real-timeapplications to such platforms to achieve an optimal trade-off between performance and power? To address those issues, this paper presents a case-study of developing and mapping embeddedapplications to a real-life Lyrtech prototyping board consisting of a TI DSP and a Xilinx Virtex-4 FPGA. A customized development flow for programming DSP and FPGA was used in our work. the measured performance and power results for different mappings of benchmarks are demonstrated. the observations that we made are also discussed to provide some empirical guidelines on using hybrid multiprocessing platforms.
Modern Intelligent Transport systems (ITS) are based on specific services that are hosted at the edge of network infrastructure. these services are created using the vehicle embeddedcomputing appliances, private clou...
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ISBN:
(纸本)9781479908462
Modern Intelligent Transport systems (ITS) are based on specific services that are hosted at the edge of network infrastructure. these services are created using the vehicle embeddedcomputing appliances, private cloud resources and global available information services. Within proposed approach all vehicles are considered as mobile part of low level operation network that providing low latency and requested QoS characteristics for ITS communication and information systems. More over some of the discussed decisions support multiprotocol interactions and predictable realtime performance so can be used for different kind of industrial, transport and robotics applications. ITS supplemented by low level operation network expands opportunity for practical implementation of emerging Internet of things (IoT) concept. thanks to wide functional ability proposed approach is well positioned for big data and on demand high performance applications. Some aspects of these services develops ideas of CISCO' Fog computing [1] and may be seamlessly supported into existing ITS cloud infrastructure using virtual firewall appliances which provides bilateral access control between vehicles that belongs to MESH network and IaaS segments resources of which support high performance computing or even supercomputers services [2].
Modern mobile computing devices are integrating more and more processing units into a single platform. For this reason separate resource managers are needed to control computing resources efectively and in an energy e...
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ISBN:
(纸本)9781479901036
Modern mobile computing devices are integrating more and more processing units into a single platform. For this reason separate resource managers are needed to control computing resources efectively and in an energy efficient way. Multimedia signal processing applications, such as a video playback, have huge variations in their resource needs depending on the input sequence characteristics. To improve this situation a resource usage estimation model has been developed and evaluated. By using the model it is possible to estimate the resource needs with less than 10% error marginal on average. A proper exploitation of prior information improves boththe user experience and the battery life. On the testing platform already a single step in the dynamic voltage and frequency scaling scheme corresponds to 30 minutes in high definition video playback time. the approach does not require changes to the existing encoders or decoders.
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