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检索条件"任意字段=13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications"

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A Hypervisor for MIPS-based Architecture Processors - a Case Study in Loongson Processors

A Hypervisor for MIPS-based Architecture Processors - a Case...

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15th ieee international conference on High Performance computing and Communications (HPCC) /11th ieee/IFIP international conference on embedded and Ubiquitous computing (EUC)

作者： Zhou, Rui Ai, Zhu Yang, Jiaming Chen, Yucong Li, Jun Zhou, Qingguo Li, Kuan-Ching Lanzhou Univ Sch Informat Sci & Engn Lanzhou 730000 Gansu Peoples R China Providence Univ Dept Comp Sci & Informat Engn CSIE Taichung Taiwan

ISBN: (纸本)9780769550886

Loongson is a family of general purpose processors based on MIPS architecture designed and manufactured in Mainland China. With the maturity of Loongson CPUs, applications are widely available with the increasing development of software tools and hardware platforms by research teams in academia and industry. In recent years, products based on Loongson have been mainly used in education, personal computers and server systems. Meanwhile, it is not yet popularly used in industrial real-time control fields, so such products have large room and potential to further development and deployment. the M-Hypervisor discussed in this paper is a real-time hypervisor designed for MIPS architecture and implemented in Loongson2F processor. It is based on the management program of para-virtualization whilst multiple partitions are scheduled to execute according to their priorities. the design and implementation of M-Hypervisor is discussed, along with details as timer, interrupts, memory management, partition loading and scheduling, to enrich real-time virtualized applications for MIPS architecture. Evaluation results show the performance and viability of proposed design, being promising to new deployments.

关键词： real-time systems hypervisor MIPS Loongson2F processor

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Performance Evaluation of the time Analysable On-Demand Coherent Cache

Performance Evaluation of the Time Analysable On-Demand Cohe...

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12th ieee international conference on Trust, Security and Privacy in computing and Communications (TrustCom)

作者： Pyka, Arthur Rohde, Mathias Uhrig, Sascha Tech Univ Dortmund Dortmund Germany

ISBN: (纸本)9780769550220

the usage of caches in multi-and many-core systems for timing critical applications is a challenging issue. time-predictability shaped up as the essential characteristic of a cache when talking about the suitability for hard real-time systems. Common cache coherence mechanisms corrupt the timing analysability of a cache memory because of unpredictable interferences between the caches. thus, these mechanisms are unsuitable for hard real-time systems. In this work, we briefly describe the ODC2 together with an extension which increases the cache hit rate. We evaluated the performance of the extended ODC2 by comparing it to analysable uncached accesses to shared data and to the well-known but unpredictable MESI and MOESI coherence techniques.

关键词： cache storage embedded systems performance evaluation

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Automated tiering in a QoS environment using coarse data

Automated tiering in a QoS environment using coarse data

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15th ieee international conference on High Performance computing and Communications (HPCC) /11th ieee/IFIP international conference on embedded and Ubiquitous computing (EUC)

作者： Lipetz, Gal Hazan, Etai Natanzon, Assaf Bachmat, Eitan Ben Gurion Univ Negev Dept Comp Sci IL-84105 Beer Sheva Israel EMC Corp Tel Aviv Israel

ISBN: (纸本)9780769550886

We present a method for providing automated performance management for a storage array with quality of service demands. Our method dynamically configures application data to heterogeneous storage devices, taking into account response time targets for the different applications. the optimization process uses widely available coarse counter statistics. We use analytical modeling of the storage system components and a gradient descent mechanism to minimize the target function. We verify the effectiveness of our optimization procedure using traces from real production systems, and show that our method improves the performance of the more significant applications, and can do so using only the coarse statistics. Our results show substantial improvements for preferred applications over an optimization procedure which does not take QoS requirements into account. We also present evidence of the complex behavior of real production storage systems, which has to be taken into account in the optimization process.

关键词： Data Reconfiguration Optimization QoS Storage systems Optimization Procedure Cache Memory System Quality of service Production systems storage devices Performance management Automation

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Critical-Path-First based allocation of real-time streaming applications on 2D mesh-type multi-cores

Critical-Path-First based allocation of real-time streaming ...

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2013 ieee 19th international conference on embedded and real-time computing systems and applications, RTCSA 2013

作者： Ali, Hazem Ismail Abdel Aziz Pinho, Luís Miguel Akesson, Benny CISTER Research Centre/INESC-TEC Polytechnic Institute of Porto Portugal Eindhoven University of Technology Netherlands

ISBN: (纸本)9781479908509

Designing cost-efficient multi-core real-time systems requires efficient techniques to allocate applications to cores while satisfying their timing constraints. However, existing approaches typically allocate using a First-Fit algorithm, which does not consider the execution time and potential parallelism of paths in the applications, resulting in over-dimensioned systems. this work addresses this problem by proposing a new heuristic algorithm, Critical-Path-First, for the allocation of real-time streaming applications modeled as dataflow graphs on 2D mesh multi-core processors. the main criteria of the algorithm is to allocate paths that have the highest impact on the execution time of the application first. It is also able to exploit parallelism in the application by allocating parallel paths on different cores. Experimental evaluation shows that the proposed heuristic improves the resource utilization by allocating up to 7% more applications and it minimizes the average end-to-end worst-case response time of the allocated applications by up to 31%. © 2013 ieee.

关键词： Heuristic algorithms

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Multicore Parallel Implementation of Agent Emotional Processes

Multicore Parallel Implementation of Agent Emotional Process...

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12th ieee international conference on Trust, Security and Privacy in computing and Communications (TrustCom)

作者： Dominguez, Carlos Hassan, Houcine Mayans, Vicent Crespo, Alfons Univ Politecn Valencia Dept Comp Engn E-46071 Valencia Spain

ISBN: (纸本)9780769550220

Emotional agents are becoming promising technologies for real-time control applications (i.e., robotics). the principal controllers of the agent are the emotional processes that decide the selection of behaviors to fulfill the objectives. the number of emotional processes increases with the complexity of the application, limiting the processing capacity of a mono-core processor to solve complex problems. A costly solution would be the use of HPC computers to solve complex problems. However, the possibilities of parallelization of the emotional processes permit their execution in parallel on multicore processors, enabling the agent to solve problems of higher complexity at a low cost. this paper presents the implementation of the emotional processes of a robotic agent in a multicore processor. To this end, the parallel emotional processes are identified and characterized, and a real-time system based on the EDF scheduling policy, to execute the emotional workload on the multicore, is proposed. In the experiments, mobile robotic applications are set-up taking into account different environmental conditions, robot dynamics and emotional states. the applications are run on multicore multithreaded processors depending on the workload requirements of the applications. Results show that only a three-core with 6 threads can tackle complex problems in the worst emotional conditions, a dual-core solves less constrained problems under normal emotional conditions and a single-core processor is only suitable for simple problems under the best conditions.

关键词： Multicore processor embedded systems real-time systems Industrial mobile robots emotional-based agents

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Hardware Acceleration for Just-In-time Compilation on Heterogeneous embedded systems

Hardware Acceleration for Just-In-Time Compilation on Hetero...

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ieee 24th international conference on Application-Specific systems, Architectures and Processors (ASAP)

作者： Carbon, Alexandre Lhuillier, Yves Charles, Henri-Pierre CEA LIST Embedded Comp Lab F-91191 Gif Sur Yvette France

ISBN: (纸本)9781479904945;9781479904938

embedded systems are increasingly complex and heterogeneous to deal with increasing performance requirements along with wider ranges of application domains. the architecture of such systems often includes different kinds of computing resources and accelerators (DSPs, GPUs, etc.). thus, application developers are facing important portability issues to adapt their software code to take maximum advantage of available processing elements. Consequently, software stacks rely more and more on virtualization technologies, leveraging Just-In-time compilation to maximize performance of applications. Nevertheless, the efficiency of Just-In-time compilation depends on the ability to compensate its overhead with execution speedups of generated code. In this paper, we propose a solution based on a dedicated processor with specialized instructions for critical functions to improve efficiency of code generators. these specialized instructions provide an average 5x speedup on manipulations of associative arrays and dynamic memory allocation. Based on the LLVM framework, we show a 15% overall speedup on code generator's execution time. Because our specialized instructions are hidden behind standard libraries, we also argue that these instructions may be transparently reused for a wider range of applications.

关键词： content-addressable storage embedded systems program compilers storage allocation virtualisation

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A Process-Based Reconfigurable SystemC Module for Simulation Speedup

A Process-Based Reconfigurable SystemC Module for Simulation...

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13th international conference on embedded Computer systems - Architectures, Modeling and Simulation (IC-SAMOS)

作者： Sotiriou-Xanthopoulos, Efstathios Siozios, Kostas Economakos, George Soudris, Dimitrios Natl Tech Univ Athens Sch Elect & Comp Engn Athens 15780 Greece

ISBN: (纸本)9781479901036

As Multi-Processor systems-on-Chip (MPSoC) architectures become more and more complex, Design Space Exploration (DSE) becomes the only viable solution for finding the pareto-optimal designs. To evaluate each solution with real dataset, DSE has to simulate the design under test, which is modeled as a Virtual Platform usually written in SystemC. However, the simulation is a very slow task which includes non-productive time periods like system initialization, while the platform re-compilation also imposes a significant overhead. In this paper, a Process-based Reconfigurable Module is used in order to bypass the non-productive simulation parts, thus accelerating the simulation. the effectiveness of the proposed methodology is proved with a series of computationally intensive multimedia applications, where the simulation time improvements reach 34% on average.

关键词： C++ language integrated circuit design multimedia communication multiprocessing systems system-on-chip virtual reality

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13th ieee international conference on BioInformatics and BioEngineering, ieee BIBE 2013

13th IEEE International Conference on BioInformatics and Bio...

引用

13th ieee international conference on BioInformatics and BioEngineering, ieee BIBE 2013

ISBN: (纸本)9781479931637

the proceedings contain 184 papers. the topics discussed include: systems genetics: experimental and computational challenges;emerging trends for decentralized e-health services in smart cities;a profile-based trust management scheme for ubiquitous healthcare environment;CloudStudy: a cloud-based system for supporting multi-centre studies;an architecture for designing future Internet (FI) applications in sensitive domains: expressing the software to data paradigm by utilizing hybrid cloud technology;quering functional brain connectomics to discover consistent subgraph patterns;a system for optically controlling neural circuits with very high spatial and temporal resolution;towards an overall 3-D vector field reconstruction via discretization and a linear equations system;a low-cost embedded real-time 3D stereo matching system for surveillance applications;and a wearable ultrasound multi-transducer array system for abdominal organs monitoring.

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embedded real-time MPC implementation using Rapid Prototyping Tools: a thermal Process case study

Embedded Real-Time MPC implementation using Rapid Prototypin...

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17th international conference System theory, Control and computing (ICSTCC)

作者： Harja, Gabriel Hernandez, Andres De Keyser, Robin Nascu, Ioan Univ Ghent Dept Elect Energy Syst & Automat B-9000 Ghent Belgium Tech Univ Cluj Napoca Dept Automat Cluj Napoca Romania

ISBN: (纸本)9781479922284;9781479922277

Recently, a strong interest has been observed in the development of new control strategies for solving optimization problems on embedded devices. Particularly, Model Predictive Control (MPC) became quite popular nowadays due to its multiple successful implementations in real-life industrial applications. the aim of this contribution is to provide practical information throughout the use of VeriStand and CompactRIO as Rapid Prototyping Tools (RPT) for implementing MPC algorithms from Matlab/Simulink code. the effectiveness of this tool is tested on a nonlinear thermal process with variable time delay, in which three different implementations of MPC to deal with both nonlinear dynamics and time delay were evaluated.

关键词： control engineering computing delays embedded systems nonlinear dynamical systems optimisation predictive control process control software prototyping

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Additive Hough Transform on embedded computing Platforms

Additive Hough Transform on Embedded Computing Platforms

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ieee 56th international Midwest Symposium on Circuits and systems (MWSCAS)

作者： Sinha, Shantanu S. Satzoda, R. K. Suchitra, S. Srikanthan, T. Indian Inst Technol Bombay 400076 Maharashtra India Nanyang Technol Univ Singapore Singapore

ISBN: (纸本)9781479900664

the Hough Transform (HT) is one of the most widely used feature extraction techniques in real-time applications, like lane departure warning, surveillance etc. Most existing HT implementations are serial in nature, resulting in high computation time. Recently, we proposed the Additive Hough Transform (AHT), which achieves angle and block level parallelism in HT computation. In this paper, we evaluate the performance gains offered by AHT in both serial and parallel configurations by implementing it on different computing platforms such as multicore processors, GPUs and FPGAs. It is shown that AHT offers significant performance gains over existing implementations of the HT in both serial and parallel configurations on a wide range of embedded platforms.

关键词： Hough transforms

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