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real-time Monitoring System for Transformer Based on GSM

Real-Time Monitoring System for Transformer Based on GSM

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4th international conference on Information computing and applications (ICICA)

作者： Zou, Li Anhui Vocat Coll Def Technol Luan Anhui Peoples R China

ISBN: (纸本)9783642539329;9783642539312

For real-time monitoring and data acquisition applications of distribution transformer, the paper put forward to wireless sensor network embedded system based on GSM, which can real-time collect and transmit data of monitoring and a variety of on-site information. Practice shows that the GSM networking solutions achieve a unified data management and user remote access based on S3C2440 chip as the core of the embedded gateway monitoring data for processing. this paper gives the system software implementation method, constructed monitoring and management information platform. through the distribution transformer factory system operating status of the actual monitoring, reliability and timeliness to meet the requirements.

关键词： GSM transformer embedded systems ARM real-time monitoring data collection

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Deploying OpenMP on an embedded Multicore Accelerator

Deploying OpenMP on an Embedded Multicore Accelerator

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13th international conference on embedded Computer systems - Architectures, Modeling and Simulation (IC-SAMOS)

作者： Agathos, Spiros N. Dimakopoulos, Vassilios V. Mourelis, Aggelos Papadogiannakis, Alexandros Univ Ioannina Dept Comp Sci GR-45110 Ioannina Greece

ISBN: (纸本)9781479901036

Multiprocessor systems-on-chip (MPSoC) are now considered first-class citizens both in the embedded systems and in the high-performance computing arenas, in the form of specialized or general-purpose accelerators. Programming models for such systems is currently a hot research topic, and as a general rule require deep programmer knowledge of the underlying hardware architecture. In this paper we present the implementation of OpenMP, one of the most intuitive and productive programming models, on the SthORM accelerator. this particular platform provides a shared-memory substrate which OpenMP requires. An innovative feature of our design is the deployment of the OpenMP model both at the host and the fabric sides, in a seamless way, which provides the programmer with a simple but effective interface for offloading and executing OpenMP kernels on the MPSoC. the optimized runtime environment provides full OpenMP support despite its small footprint (less than 10KB for a 16-core cluster) and can sustain close-to-ideal speedups in computationally intensive applications. We detail on design issues we faced along with their solutions, given the limited available resources.

关键词： embedded systems multiprocessing systems shared memory systems system-on-chip

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An embedded Hardware-Efficient Architecture for real-time Cascade Support Vector Machine Classification

An Embedded Hardware-Efficient Architecture for Real-Time Ca...

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13th international conference on embedded Computer systems - Architectures, Modeling and Simulation (IC-SAMOS)

作者： Kyrkou, Christos theocharides, theocharis Bouganis, Christos-Savvas Univ Cyprus KIOS Res Ctr Dept Elect & Comp Engn Nicosia Cyprus Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England

ISBN: (纸本)9781479901036

Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, especially when considering embedded applications. Cascade SVMs have been proposed in an attempt to speed-up classification times, but improved performance comes at a cost of additional hardware resources. Consequently, in this paper we propose an optimized architecture for cascaded SVM processing, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings for embedded applications. the architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640x480 resolution images. Additionally, it was compared against implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. the proposed architecture achieves an average performance of 70 frames-per-second, demonstrating a speed-up of 5x over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less hardware resources and a 20% reduction in power, with only 0.7% reduction in classification accuracy.

关键词： Field Programmable Gate Arrays Support Vector Machines Cascade Classifier real-time and embedded systems Parallel Architecture

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timeCube: A Manycore embedded Processor with Interference-Agnostic Progress Tracking

TimeCube: A Manycore Embedded Processor with Interference-Ag...

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13th international conference on embedded Computer systems - Architectures, Modeling and Simulation (IC-SAMOS)

作者： Gupta, Anshuman Sampson, Jack Taylor, Michael Bedford Univ Calif San Diego San Diego CA 92103 USA

ISBN: (纸本)9781479901036

Recently introduced processors such as Tilera's Tile Gx100 and Intel's 48-core SCC have delivered on the promise of high performance per watt in manycore processors, making these architectures ostensibly as attractive for low-power embedded processors as for cloud services. However, these architectures space-multiplex the microarchitectural resources between many threads to increase utilization, which leads to potentially large and varying levels of interference. this decorrelates CPU-time from actual application progress and decreases the ability of traditional software to accurately track and finely control application progress, hindering the adoption of manycore processors in embedded computing. In this paper we propose Progress time as the counterpart of CPU-time in space-multiplexed systems and show how it can be used to track application progress. We also introduce timeCube, a manycore embedded processor that uses dynamic execution isolation and shadow performance modeling to provide an accurate online measurement of each application's Progress time. Our evaluation shows that a 32-core timeCube processor can track application progress with less than 1% error even in the presence of a 6x average worst-case slowdown. timeCube also uses Progress times to perform online architectural resource management that leads to a 36% improvement in throughput compared to existing microarchitectural resource allocation schemes. Overall, the results argue for adding the requisite microarchitectural structures to support Progress time in manycore chips for embedded systems.

关键词： cloud computing embedded systems interference microprocessor chips multiprocessing systems resource allocation

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Parallel Implementation of real-time Semi-Global Matching on embedded Multi-Core Architectures

Parallel Implementation of Real-Time Semi-Global Matching on...

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13th international conference on embedded Computer systems - Architectures, Modeling and Simulation (IC-SAMOS)

作者： Arndt, Oliver Jakob Becker, Daniel Banz, Christian Blume, Holger Leibniz Univ Hannover Inst Microelect Syst D-30167 Hannover Germany Corporate Techn D-81739 Munich Germany

ISBN: (纸本)9781479901036

embedded real-time algorithms are often realized with dedicated hardware, exhibiting high production costs and low programming flexibility thereafter. For instance, semi-global matching for stereo image processing, including complex data flows, traditionally runs on customized hardware modules. Combining the processing and memory capabilities of multiple individual cores, emerging embedded multi-core technologies address these problems. However, considering concurrency issues (e. g., data races and lock contentions), parallel programming requires experienced programmers and technology-specific techniques (e. g., synchronization libraries) and tools (e. g., parallel profilers), which are often not available on embedded platforms. In this work, we introduce a parallel version of a semi-global matching algorithm and demonstrate within this case study runtime optimizations necessary to meet real-time requirements. We also show structured steps of the applied parallelization workflow, illustrating an efficient migration strategy to multi-core platforms using runtime information (e. g., profiles and hardware counters). Finally, to evaluate the resulting performance characteristics, we compare the runtime behavior of the parallel version running on a Freescale P4080 processor with reference values taken on an Intel i7, a field-programmable logic device, an extended general purpose processor and a GPU.

关键词： concurrency control embedded systems image matching multiprocessing systems parallel architectures parallel programming performance evaluation

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Concurrent Multi-level Arrays: Wait-free Extensible Hash Maps

Concurrent Multi-level Arrays: Wait-free Extensible Hash Map...

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13th international conference on embedded Computer systems - Architectures, Modeling and Simulation (IC-SAMOS)

作者： Feldman, Steven LaBorde, Pierre Dechev, Damian Univ Cent Florida Dept Elect Engn & Comp Sci Orlando FL 32816 USA

ISBN: (纸本)9781479901036

In this work we present the first design and implementation of a wait-free hash map. Our multiprocessor data structure allows a large number of threads to concurrently put, get, and remove information. Wait-freedom means that all threads make progress in a finite amount of time - an attribute that can be critical in real-time environments. this is opposed to the traditional blocking implementations of shared data structures which suffer from the negative impact of deadlock and related correctness and performance issues. Our design is portable because we only use atomic operations that are provided by the hardware;therefore, our hash map can be utilized by a variety of data-intensive applications including those within the domains of embedded systems and supercomputers. the challenges of providing this guarantee make the design and implementation of wait-free objects difficult. As such, there are few wait-free data structures described in the literature;in particular, there are no wait-free hash maps. It often becomes necessary to sacrifice performance in order to achieve wait-freedom. However, our experimental evaluation shows that our hash map design is, on average, 5 times faster than a traditional blocking design. Our solution outperforms the best available alternative non-blocking designs in a large majority of cases, typically by a factor of 8 or higher.

关键词： concurrency control data structures multiprocessing systems

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Design of real-time Encryption Module for Secure Data Protection of Wearable Healthcare Devices

Design of Real-time Encryption Module for Secure Data Protec...

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35th Annual international conference of the ieee-Engineering-in-Medicine-and-Biology-Society (EMBC)

作者： Kim, Jungchae Lee, Byuck Jin Yoo, Sun K. Yonsei Univ Grad Programs Biomed Engn Seoul 120749 South Korea

ISBN: (纸本)9781457702167

Wearable devices for biomedical instrumentation could generate the medical data and transmit to a repository on cloud service through wireless networks. In this process, the private medical data will be disclosed by man in the middle attack. thus, the archived data for healthcare services would be protected by non-standardized security policy by healthcare service provider (HSP) because HIPAA only defines the security rules. In this paper, we adopted the Advanced Encryption Standard (AES) for security framework on wearable devices, so healthcare applications using this framework could support the confidentiality easily. the framework developed as dynamic loadable module targeted for lightweight microcontroller such as msp430 within embedded operating system. the performance was shown that the module can support the real-time encryption using electrocardiogram and photoplethysmogram. In this regard, the processing load for enabling security is distributed to wearable devices, and the customized data protection method could be composed by HSP for a trusted healthcare service.

关键词： biomedical equipment cryptography data privacy electrocardiography embedded systems health care medical computing microcontrollers operating systems (computers) photoplethysmography trusted computing

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real-time Smooth Task Transitions for Hierarchical Inverse Kinematics 13

Real-Time Smooth Task Transitions for Hierarchical Inverse K...

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13th ieee-RAS international conference on Humanoid Robots (Humanoids)

作者： Jarquin, Gerardo Escande, Adrien Arechavaleta, Gustavo Moulard, thomas Yoshida, Eiichi Parra-Vega, Vicente IPN Ctr Invest Estudios Avanzados Robot & Adv Mfg Grp Saltillo Coahuila Mexico CNRS AIST JRL UMI3218 CRT F-75700 Paris France

ISBN: (纸本)9781479926190

Hierarchical inverse kinematics (HIK) is widely used for generating feasible velocity trajectories that serve as input references for highly redundant robots such as humanoid robots. To generate the velocity trajectories a set of prioritized tasks should be provided. For some applications, it is not necessary to change the priority order of the tasks in the stack of tasks (SoT) along the motion execution. However, complex tasks need a dynamic behavior of the SoT such that the insertion, removal or swap can be performed at running time. these task transitions may induce discontinuities in the joint velocities if they are not carefully handled. In this context, we propose an efficient strategy to manage task transitions through a simple procedure which smoothly interchange the priority of a couple of consecutive prioritized tasks. Furthermore, our method does not increase the computational cost of the HIK since neither any additional task should be added, nor parallel control laws should be computed. As a result our strategy may be used in real time to produce the velocity commands of real humanoid robots. the effectiveness of our strategy is verified at simulation level with the HRP-2 humanoid robot performing complex time-driven tasks.

关键词： humanoid robots motion control robot kinematics trajectory control velocity control HIK HRP-2 humanoid robot SoT dynamic behavior hierarchical inverse kinematics motion execution parallel control law priority order real humanoid robot real-time smooth task transition redundant robot stack of task velocity commands velocity trajectory Computational efficiency Humanoid robots Joints Kinematics Null space real-time systems

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An Efficient Fault Recovery Algorithm in Multiprocessor Mixed-Criticality systems

An Efficient Fault Recovery Algorithm in Multiprocessor Mixe...

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15th ieee international conference on High Performance computing and Communications (HPCC) /11th ieee/IFIP international conference on embedded and Ubiquitous computing (EUC)

作者： Liu, Guangdong Lu, Ying Wang, Shige Univ Nebraska Dept Comp Sci & Engn Lincoln NE 68588 USA Gen Motor Global Res & Dev Elect & Controls Integrat Lab Warren MI USA

ISBN: (纸本)9780769550886

Recent years, there is an increasing interest of integrating mixed-criticality functionalities onto a shared computing platform in automotive, avionics and the control industry. the benefits of such an integration include reduced hardware cost and high computational performance. Also, new challenges appear as a result of the integration since interferences across tasks with different criticalities are introduced and these interferences could potentially lead to catastrophic results. Failures are likely to be more frequent due to the interferences. Hence, it is becoming increasingly important to deal with faults in mixed-criticality systems. Although several approaches have been proposed to handle failures in mixed-criticality systems, they come either with a high cost due to a hardware replication (spatial redundancy) or with a poor utilization due to reexecution (time redundancy). In this paper, we study a scheme that provides fault recovery through task reallocations in response to permanent faults in multiprocessor mixed-criticality systems. We present an algorithm to minimize the number of task reallocations while retaining the promise that the most critical applications continue to meet their deadlines. the performance evaluation of the proposed algorithm is carried out by comparing it with two baseline algorithms. In order to evaluate the performance of algorithms from the perspective of mixed-criticality systems, we choose the state of art metric called ductility to formally measure the effects of deadline misses for tasks with different criticality levels. Under this metric, a high-criticality task is considered more important than all low-criticality tasks combined. the simulation results confirm the effectiveness of our proposed algorithm in both minimizing the number of task reallocations and retaining the promised performance of high-criticality tasks.

关键词： fault recovery multiprocessor mixed-criticality real-time systems task reallocation failure recovery Multiprocessor Religious Missions permanent fault algorithms DNA Integration integration

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SLOAVx: Scalable LOgarithmic AlltoallV Algorithm for Hierarchical Multicore systems 13

SLOAVx: Scalable LOgarithmic AlltoallV Algorithm for Hierarc...

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13th ieee/ACM international Symposium on Cluster, Cloud, and Grid computing (CCGrid)

作者： Xu, Cong Venkata, Manjunath Gorentla Graham, Richard L. Wang, Yandong Liu, Zhuo Yu, Weikuan Auburn Univ Auburn AL 36849 USA Oak Ridge Natl Lab Oak Ridge TN USA

ISBN: (纸本)9780769549965;9781467364652

Scientific applications use collective communication operations in Message Passing Interface (MPI) for global synchronization and data exchanges. Alltoall and AlltoallV are two important collective operations. they are used by MPI jobs to exchange messages among all of MPI processes. AlltoallV is a generalization of Alltoall, supporting messages of varying sizes. However, the existing MPI AlltoallV implementation has linear complexity, i.e., each process has to send messages to all other processes in the job. Such linear complexity can result in suboptimal scalability of MPI applications when they are deployed on millions of cores. To address above challenge, in this paper, we introduce a new Scalable LOgarithmic AlltoallV algorithm, named SLOAV, for MPI AlltoallV collective operation. SLOAV aims to achieve global exchange of small messages of different sizes in a logarithmic number of rounds. Furthermore, given the prevalence of multicore systems with shared memory, we design a hierarchical AlltoallV algorithm based on SLOAV by leveraging the advantages of shared memory, which is referred to as SLOAVx. Compared to SLOAV, SLOAVx significantly reduces the inter-node communication, thus improving the entire system performance and mitigating the impact of message latency. We have implemented and embedded both algorithms in Open MPI. Our evaluation on large-scale computer systems shows that for the 8-byte and 1024-process MPI_Alltoallv operation, the SLOAV can reduce the latency by as much as 86.4%, when compared to the state-of-the-art, and SLOAVx can further optimize the SLOAV by up to 83.1% in terms of message latency on multicore systems. In addition, experiments with NAS Parallel Benchmark (NPB) demonstrate that our algorithms are very effective for real-world applications.

关键词： MPI AlltoallV Algorithm Collectives Scalability

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