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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

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Incident Response Probabilistic Cognitive Maps

Incident Response Probabilistic Cognitive Maps

引用

international symposium on parallel and distributed processing with applications, ISPA

作者： Jihene Krichene Noureddine Boudriga University of 7th of November Tunisia

Security incident response is a major activity to guarantee the protection of information systems. We develop in this paper a methodology for automatically determining responses to security incidents based on a new category of cognitive maps, referred to as incident response probabilistic cognitive map. the main issue addressed in this paper is the development of a methodology using mathematical tools for reasoning about the constructed cognitive map to identify the attack, to reduce its complexity, and to search for the decision responding to the detected attack. the main features have been highlighted showing the complexity of the incident response team role.

关键词： Intrusion detection Information security Intelligent sensors Formal languages distributed processing Protection Information systems Decision making Fuzzy cognitive maps Gas detectors

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DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor

DMA Performance Analysis and Multi-core Memory Optimization ...

引用

international symposium on parallel and distributed processing with applications, ISPA

作者： Yong Dou Lin Deng Jinhui Xu Yi Zheng National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha Hunan China

the Cell processor is a typical heterogeneous multi-core processor, which owns powerful computing capability. But we are facing the challenges of 'memory wall' in developing parallel applications, such as, limited capacity of local memory, limited memory bandwidth for multi-cores and the long latency for data communication. the DMA transfer mechanism is often used to hide the long latency and improve the effective usage of memory bandwidth. In the paper, we start with a series of DMA experimental tests in the context of the Cell processor architecture, and perform mathematical analysis to setup a unified formula on the average bandwidth of DMA by means of exponential fitting, which describes that SPE amount and DMA block size take main effects on DMA bandwidth in quantity. With the supports of the DMA performance formula, we perform 4 types of memory optimization in the process of parallelizing the SWIM benchmark program into a multi-core version. We take Sony PlayStation 3 (PS3) as our test-bed. For SWIM benchmark, with 6 SPE cores, we obtain over 13 times of speedup compared to single PPE, and 3.3 to 6.18 times to AMD and Intel CPU.

关键词： Performance analysis Bandwidth Delay Benchmark testing Multicore processing Data communication Context Performance evaluation Mathematical analysis Fitting

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FlexPar: Reconfigurable Middleware for parallel Environments

FlexPar: Reconfigurable Middleware for Parallel Environments

引用

international symposium on Object-Oriented Real-Time distributed Computing

作者： Jó Ueyama Edmundo Roberto Mauro Madeira Paul Grace Institute de Computaçao Universidade Estadual de Compinsa (UNICAMP) Sao Paulo Brazil Computing Department Lancaster university Lancaster UK

ISBN: (纸本)9780769531328

Although a growing number of devices have the support for parallel processing, parallelism is not widely exploited, as it should be. this can be illustrated by the fact that all Apple desktops and laptops are currently supplied with one or more dual- core processors. Despite this, parallel programming in popular languages such as Java is not widely encouraged and often only recommended as a last resort. In addition, it is likely that the next generation parallel applications will have to operate within a diverse range of heterogeneous devices ranging from supercomputers to sensors. this paper proposes a flexible component-based middleware that aims at facilitating the construction of deadlock-free parallel and concurrent applications for heterogeneous environments. the middleware is particularly targeted to tailor applications to the target need and environment. For our prototyping, we implemented plu- gins that are capable of deploying JCSP (CSP library for Java programmers) and OCCam-pi processes. Both JCSP and OCCam-pi make use of the CSP disciplines. the CSP (Communicating Sequential Processes) paradigm helps us to avoid concurrency problems such as deadlocks. It should be stressed that there is no bias towards these languages as the proposed middleware is highly extensible.

关键词： Middleware Java System recovery parallel processing Portable computers Current supplies parallel programming Supercomputers Prototypes Libraries

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distributed online anomaly detection in high-content screening

Distributed online anomaly detection in high-content screeni...

引用

ieee international symposium on Biomedical Imaging

作者： Adam Goode Rahul Sukthankar Lily Mummert Mei Chen Jeffrey Saltzman David Ross Stacey Szymanski Anil Tarachandani M. Satyanarayanan Carnegie Mellon University USA Intel Research Pittsburgh Merck and Company Inc.

this paper presents an automated, online approach to anomaly detection in high-content screening assays for pharmaceutical research. Online detection of anomalies is attractive because it offers the possibility of immediate corrective action, early termination, and redesign of assays that may require many hours or days to execute. the proposed approach employs assay-specific image processing within an assay-independent framework for distributed control, machine learning, and anomaly reporting. Specifically, we exploit coarse-grained parallelism to distribute image processing over several computing nodes while efficiently aggregating sufficient statistics across nodes. this architecture also allows us to easily handle geographically-distributed data sources. Our results from two applications, adipocyte quantitation and neurite growth estimation, confirm that this online approach to anomaly detection is feasible, efficient, and accurate.

关键词： Image processing Pharmaceuticals Termination of employment distributed control Machine learning parallel processing Concurrent computing distributed computing Statistical distributions Computer architecture

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DC-SIMD : Dynamic communication for SIMD processors

DC-SIMD : Dynamic communication for SIMD processors

引用

international symposium on parallel and distributed processing (IPDPS)

作者： Raymond Frijns Hamed Fatemi Bart Mesman Henk Corporaal Eindhovan University of Technology Eindhoven Noord-Brabant Netherlands

SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the huge amount of data-level parallelism in pixel-type operations, operating at a relatively low energy consumption rate. However, current SIMD architectures lack support for dynamic communication between processing elements, which is needed to efficiently map a set of non-linear algorithms. An architecture for dynamic communication support has been proposed, but this architecture needs large amounts of buffering to function properly. In this paper, three architectures supporting dynamic communication without the need of large amounts of buffering are presented, requiring 98% less buffer space. Cycle-true communication architecture simulators have been developed to accurately predict the performance of the different architectures. Simulations with several test algorithms have shown a performance improvement of up to 5x compared to a locally connected SIMD-processor. Also, detailed area models have been developed, estimating the three proposed architectures to have an area overhead of 30-70% compared to a locally connected SIMD architecture (like the IMAP). When memory is taken into account as well, the overhead is estimated to be 13-28%.

关键词： Computer architecture Process control Image processing Smart cameras parallel processing Pixel Costs Registers Energy consumption Predictive models

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Modeling and predicting application performance on parallel computers using HPC challenge benchmarks

Modeling and predicting application performance on parallel ...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： Wayne Pfeiffer Nicholas J. Wright San Diego Supercomputer Center La Jolla CA USA

A method is presented for modeling application performance on parallel computers in terms of the performance of microkernels from the HPC Challenge benchmarks. Specifically, the application run time is expressed as a linear combination of inverse speeds and latencies from microkernels or system characteristics. the model parameters are obtained by an automated series of least squares fits using backward elimination to ensure statistical significance. If necessary, outliers are deleted to ensure that the final fit is robust. Typically three or four terms appear in each model: at most one each for floating-point speed, memory bandwidth, interconnect bandwidth, and interconnect latency. Such models allow prediction of application performance on future computers from easier-to-make predictions of microkernel performance. the method was used to build models for four benchmark problems involving the PARATEC and MILC scientific applications. these models not only describe performance well on the ten computers used to build the models, but also do a good job of predicting performance on three additional computers with newer design features. For the four application benchmark problems with six predictions each, the relative root mean squared error in the predicted run times varies between 13 and 16%. the method was also used to build models for the HPL and G-FFTE benchmarks in HPCC, including functional dependences on problem size and core count from complexity analysis. the model for HPL predicts performance even better than the application models do, while the model for G-FFTE systematically underpredicts run times.

关键词： Predictive models Application software Concurrent computing Delay Bandwidth Extrapolation High performance computing Supercomputers Least squares methods Robustness

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Spatial awareness of digital artefacts 07

Spatial awareness of digital artefacts

引用

11th ieee international symposium on distributed Simulation and Real-Time applications, DS-RT 2007

作者： Ferscha, Alois Institut für Pervasive Computing Johannes Kepler Universität Linz Altenberger Strasse 69 A-4040 Linz Austria

No abstract available

ISBN: (纸本)0769530117

No abstract available

关键词： Peer to peer computing Pervasive computing Computational modeling Wireless sensor networks Wireless communication Computer science distributed computing Performance analysis Application software Home appliances

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Implementation of distributed application using RMI Java threads

Implementation of distributed application using RMI Java thr...

引用

7th ieee international symposium on Signal processing and Information Technology

作者： Keshk, Arabi E. Menoufia Univ Fac Comp & Informat Menoufia Egypt

ISBN: (纸本)9781424418343

In this paper, we suggest a mechanism for implementing a distributed application using RMI based on JAVA threads. the application is parallel matrices multiplication depending on distributed the products of rows and columns on different machines. One server and three clients are run to find the product of matrix multiplication. the server distributes the determine blocks of rows and columns on the registered clients. the clients return their product blocks to a server, which calculate the final product of matrix multiplication. applications of this type will allow loaded servers to transfer part of the load to clients to exploit the computing power available at client side. the time Of matrix multiplication with size of 256 x 256 is reduced by 52.5% by using 3-client and this time can be decreased more in the case of increasing the number of clients.

关键词： Computing power

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distributed virtual reality in education 07

Distributed virtual reality in education

引用

11th ieee international symposium on distributed Simulation and Real-Time applications, DS-RT 2007

作者： Kaufmann, Hannes Vienna University of Technology Interactive Media Systems Group Vienna Austria Institute of Software Technology and Interactive Systems Vienna University of Technology VR Group

ISBN: (纸本)0769530117

Educational virtual reality (VR) applications have a huge potential to support learning and teaching. A brief overview of previous educational VR applications will be followed by a summary of requirements specific to this field. In a typical collaborative classroom situation where large groups of users must be supported, as well as in distance education, robust and reliable networked environments are of primary importance. the speaker will present Construct3D, an application for geometry education that has been developed at the VR group at Vienna University of Technology throughout the past 6 years. Specific design aspects to allow distributed collaboration in Construct3D are presented. this concerns improvements of the user interface, usability and system performance including bandwidth efficiency. the results of three evaluations, some of them in co-located and distributed setups, with a total of more than 500 students in over 300 teaching lessons will be presented. © 2007 ieee.

关键词： Virtual reality

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Optimization of area and performance by processor-like reconfiguration

Optimization of area and performance by processor-like recon...

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21st international parallel and distributed processing symposium, IPDPS 2007

作者： Oppold, Tobias Eisenhardt, Sven Rosenstiel, Wolfgang Department of Computer Engineering University of Tuebingen Sand 13 72076 Tuebingen Germany

ISBN: (纸本)1424409101

It is well known that the area efficiency of a digital circuit can be improved by reconfiguration due to the reuse of resources. In this paper, we show that this benefit can be achieved for a wide range of applications if the reconfiguration can take place within each clock cycle, and we quantify the benefit by area estimations from a synthesizable architecture model. Although reconfiguration typically involves a decrease of performance, we show how performance can actually be increased by redirecting communication through the time domain. this increase is quantified by estimations from a silicon-proven commercial architecture and its associated compiler. ©2007 ieee.

关键词： Program processors

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