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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

共 2575 条记录，以下是1721-1730 订阅

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Algorithmic skeletons for stream programming in embedded heterogeneous parallel image processing applications 20

Algorithmic skeletons for stream programming in embedded het...

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20th ieee international parallel and distributed processing symposium, IPDPS 2006

作者： Caarls, W. Jonker, P.P. Corporaal, H. Delft University of Technology Quantitative Imaging Group Lorentzweg 1 Delft Netherlands Eindhoven University of Technology Dept. of Electrical Engineering Den Dolech 2 Eindhoven Netherlands

ISBN: (纸本)1424400546

Algorithmic skeletons can be used to write architecture independent programs, shielding application developers from the details of a parallel implementation. In this paper, we present a C-like skeleton implementation language, PEPCI, that uses term rewriting and partial evaluation to specify skeletons for parallel C dialects. By using skeletons to control the iteration of kernel functions, we provide a stream programming language that is better tailored to the user as well as the underlying architecture. Skeleton merging allows us to reduce the overheads usually associated with breaking an application into small kernels. We have implemented an example image processing application on a heterogeneous embedded prototype platform consisting of an SIMD and ILP processor, and show that a significant speedup can be achieved without requiring knowledge of data parallel processing. © 2006 ieee.

关键词： Image processing

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MPI-Mitten: Enabling migration technology in MPI 06

MPI-Mitten: Enabling migration technology in MPI

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6th ieee international symposium on Cluster Computing and the Grid (CCGRID 2006)

作者： Du, Cong Sun, Xian-He IIT Dept Comp Sci Chicago IL 60616 USA

ISBN: (纸本)0769525857

Group communications are commonly used in parallel and distributed environment. However, existing migration mechanisms do not support group communications. this weakness prevents migration-based proactive fault tolerance, among others, to be applied to MPI applications. In this study, we propose distributed migration protocols with group membership management to support process migration with group changing. We design and implement a process migration enabling MPI library, named MPI-Mitten, to verify the protocols and enhance current MPI platforms for reliability and usability. MPI-Mitten is based on MPI standard and can be applied to any MPI-2 implementations. Experimental results show the proposed distributed process migration protocols are solid and the MPI-Mitten system is effective and is uniquely supporting migration-based fault tolerance.

关键词： Fault tolerance Hardware Protocols Supercomputers Sun Libraries Usability parallel processing Computer science Application software

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A framework to develop symbolic performance models of parallel applications 20

A framework to develop symbolic performance models of parall...

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20th ieee international parallel and distributed processing symposium, IPDPS 2006

作者： Alam, Sadaf R. Vetter, Jeffrey S. Oak Ridge National Laboratory Oak Ridge TN 37831 United States

ISBN: (纸本)1424400546

Performance and workload modeling has numerous uses at every stage of the high-end computing lifecycle: design, integration, procurement, installation and tuning. Despite the tremendous usefulness of performance models, their construction remains largely a manual, complex, and time-consuming exercise. We propose a new approach to the model construction, called modeling assertions (MA), which borrows advantages from both the empirical and analytical modeling techniques. this strategy has many advantages over traditional methods: incremental construction of realistic performance models, straightforward model validation against empirical data, and intuitive error bounding on individual model terms. We demonstrate this new technique on the NAS parallel CG and SP benchmarks by constructing high fidelity models for the floating-point operation cost, memory requirements, and MPI message volume. these models are driven by a small number of key input parameters thereby allowing efficient design space exploration of future problem sizes and architectures. © 2006 ieee.

关键词： parallel processing systems

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A scalable algorithm to monitor Chord-based P2P systems at runtime 20

A scalable algorithm to monitor Chord-based P2P systems at r...

引用

20th ieee international parallel and distributed processing symposium, IPDPS 2006

作者： Binzenhöfer, Andreas Kunzmann, Gerald Henjes, Robert University of Würzburg Institute of Computer Science Am Hubland 97074 Würzburg Germany Technische Universitaet Muenchen Institute of Communication Networks 80290 Munich Germany

ISBN: (纸本)1424400546

Peer-to-peer (p2p) systems are a highly decentralized, fault tolerant, and cost effective alternative to the classic client-server architecture. Yet companies hesitate to use p2p algorithms to build new applications. Due to the decentralized nature of such a p2p system the carrier does not know anything about the current size, performance, and stability of its application. In this paper we present an entirely distributed and scalable algorithm to monitor a running p2p network. the snapshot of the system enables a telecommunication carrier to gather information about the current performance parameters of the running system as well as to react to discovered errors. © 2006 ieee.

关键词： distributed computer systems

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An adaptive system-on-chip for network applications 20

An adaptive system-on-chip for network applications

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20th ieee international parallel and distributed processing symposium, IPDPS 2006

作者： Koch, Roman Pionteck, thilo Albrecht, Carsten Maehle, Erik University of Lübeck Institute of Computer Engineering 23538 Lübeck Germany

ISBN: (纸本)1424400546

this paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor for offloading computationally intensive tasks from a network processor. the system-on-chip architecture is based on an adaptable network-on-chip which allows the dynamic replacement of hardware modules as well as the adaptation of the on-chip communication structure. the coprocessor leverages the active partial reconfiguration feature of modern FPGAs in order to adapt to shifting demand patterns. An embedded general-purpose processor core within the coprocessor runs software which manages the configurations of the device. With reference to a prototypical implementation targeting a Xilinx Virtex-II Pro FPGA, this paper focuses on on-chip communication issues. Topics include the integration of PowerPC processor cores into the configurable logic as well as the mode of operation of the network-on-chip. © 2006 ieee.

关键词： Chip scale packages

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An extensible global address space framework with decoupled task and data abstractions 20

An extensible global address space framework with decoupled ...

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20th ieee international parallel and distributed processing symposium, IPDPS 2006

作者： Krishnamoorthy, Sriram Catalyurek, Umit Nieplocha, Jarek Rountev, Atanas Sadayappan, P. Dept. of Computer Science and Engineering Ohio State University Columbus OH 43210 United States Dept. of Biomedical Informatics Ohio State University Columbus OH 43210 United States Computational Sciences and Mathematics Pacific Northwest National Laboratory Richland WA 99352 United States

ISBN: (纸本)1424400546

Although message passing using MPI is the dominant model for parallel programming today, the significant effort required to develop high-performance MPI applications has prompted the development of several parallel programming models that are more convenient. Programming models such as Co-Array Fortran, Global Arrays, Titanium, and UPC provide a more convenient global view of the data, but face significant challenges in delivering high performance over a range of applications. It is particularly challenging to achieve high performance using global-address-space languages for unstructured applications with irregular data structures. In this paper, we describe a global-address-space parallel programming framework with decoupled task and data abstractions. the framework centers around the use of task pools, where tasks specify operands in a distributed, globally addressable pool of data chunks. the data chunks can be addressed in a logical multi-dimensional "tuple" space, and are distributed among the nodes of the system. Locality-aware load balancing of tasks in the task pool is achieved through judicious mapping via hyper-graph partitioning, as well as dynamic task/data migration. the framework implements a transparent interface for out-of-core data, so that explicit orchestration of movement of data between disks and memory is not required of the programmer. the use of the framework for implementation of parallel blocksparse tensor computations in the context of a quantum chemistry application is illustrated. © 2006 ieee.

关键词： parallel processing systems

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Integrated link/CPU voltage scaling for reducing energy consumption of parallel sparse matrix applications 20

Integrated link/CPU voltage scaling for reducing energy cons...

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20th ieee international parallel and distributed processing symposium, IPDPS 2006

作者： Son, Seung Woo Malkowski, Konrad Chen, Guilin Kandemir, Mahmut Raghavan, Padma Pennsylvania State University Department of Computer Science and Engineering University Park PA 16802 United States

ISBN: (纸本)1424400546

Reducing power consumption is quickly becoming a first-class optimization metric for many high-performance parallel computing platforms. One of the techniques employed by many prior proposals along this direction is voltage scaling and past research used it on different components such as networks, CPUs, and memories. In contrast to most of the existent efforts on voltage scaling that target a single component (CPU, network or memory components), this paper proposes and experimentally evaluates a voltage/frequency scaling algorithm that considers CPU and communication links in a mesh network at the same time. More specifically, it scales voltages/frequencies of both CPUs in the network and the communication links among them in a coordinated fashion (instead of one after another) such that energy savings are maximized without impacting execution time. Our experiments with several tree-based sparse matrix computations reveal that the proposed integrated voltage scaling approach is very effective in practice and brings 13% and 17% energy savings over the pure CPU and pure communication link voltage scaling schemes, respectively. the results also show that our savings are consistent with the different network sizes and different sets of voltage/frequency levels. © 2006 ieee.

关键词： Computer architecture

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Towards a sophisticated grid workflow development and computing environment 20

Towards a sophisticated grid workflow development and comput...

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20th ieee international parallel and distributed processing symposium, IPDPS 2006

作者： Fahringer, thomas University of Innsbruck Institute for Computer Science Technikerstr. 21 a A-6020 Innsbruck Austria

ISBN: (纸本)1424400546

While Grid infrastructures can provide massive compute and data storage power, it is still an art to effectively harness the power of Grid computing. Current application development for Grid commonly requires the programmer to deal with many low level and complex details such as selecting software components on specific Grid computers, mapping applications onto the Grid, explicitly specify data transfer operations, etc. In this talk we will present the ASKALON environment whose goal is to create an invisible Grid for both Grid users and application developers. ASKALON is centered around a set of high-level services for transparent and effective Grid access, including a Scheduler for optimized mapping of workflows onto the Grid, an Enactment Engine for reliable application execution, a Resource Manager covering both computers and application components, and a Performance Prediction and Analysis service based on a traing phase, analytical models and dynamic measurements. A sophisticated XML-based programming interface that shields the user form the Grid middleware details, allows the high-level composition of workflow applications. ASKALON is used to develop and port scientific applications as workflows in the Austrian Grid. Experimental results using several real-world scientific applications to demonstrate the effectiveness of ASKALON will be demonstrated. © 2006 ieee.

关键词： parallel processing systems

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Real-time task mapping and scheduling for collaborative In-network processing in DVS-enabled wireless sensor networks 20

Real-time task mapping and scheduling for collaborative In-n...

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20th ieee international parallel and distributed processing symposium, IPDPS 2006

作者： Tian, Yuan Boangoat, Jarupan Ekici, Eylem Özgüner, Füüsun Department of Electrical and Computer Engineering Ohio State University United States

ISBN: (纸本)1424400546

With the increasing importance of energy consumption considerations and new requirements of emerging applications, in-network processing of information gains recognition as a viable solution for Wireless Sensor Networks (WSNs). the required processing capability can be achieved through locally collaborative information processing among sensors. Task mapping and scheduling plays an important role in efficient collaborative information processing. Although task mapping and scheduling in wired networks of processors has been well studied in the past, its counterpart for WSNs remains largely unexplored. In this paper, a task mapping and scheduling solution for real-time applications in WSNs, Real-time Task Mapping and Scheduling (RT-MapS), is presented. RT-MapS incorporates wireless channel modeling, Hyper-DAG extension, concurrent task mapping, communication and computation scheduling, and Dynamic Voltage Scaling (DVS) methods. Simulation results show significant performance improvements compared with existing mechanisms in terms of providing deadline guarantee with minimum energy consumption. © 2006 ieee.

关键词： Mapping

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Power-performance efficiency of asymmetric multiprocessors for multi-threaded scientific applications 20

Power-performance efficiency of asymmetric multiprocessors f...

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20th ieee international parallel and distributed processing symposium, IPDPS 2006

作者： Grant, Ryan E. Afsahi, Ahmad Department of Electrical and Computer Engineering Queen's University Kingston Ont. K7L 3N6 Canada

ISBN: (纸本)1424400546

Recently, under a fixed power budget, asymmetric multiprocessors (AMP) have been proposed to improve the performance of multi-threaded applications compared to symmetric multiprocessors. An AMP is a multiprocessor system in which its processors are not operating at the same frequency. Power consumption has become an important design constraint in servers and high-performance server clusters. this paper explores the power-performance efficiency of Hyper-threaded (HT) AMP servers, and proposes a new scheduling algorithm that can be used to reduce the overall power consumption of a server while maintaining a high level of performance. Prototyping AMPs on a commercial 4-way SMP server, we show that on average 15.6% energy savings and 6.1% slowdown for the HT-disabled case, and 7.1% energy savings and 4.8% slowdown for the HT-enabled case can be achieved across NAS and SPEC OpenMP applications. © 2006 ieee.

关键词： Multiprocessing systems

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