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Energy efficient multi-hop polling in clusters of two-layered heterogeneous sensor networks

Energy efficient multi-hop polling in clusters of two-layere...

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19th ieee international parallel and distributed processing symposium, IPDPS 2005

作者： Zhang, Zhenghao Ma, Ming Yang, Yuanyuan Department of Electrical and Computer Engineering State University of New York Stony Brook NY 11794 United States

ISBN: (纸本)0769523129

In this paper we study two-layered heterogeneous sensor networks where two types of nodes are deployed in the network: basic sensor nodes and cluster head nodes. Basic sensor nodes are simple and inexpensive, while cluster head nodes are much powerful and much richer in energy. A cluster head node organizes the basic sensor nodes around it into a cluster. A basic sensor node does data collections and sends the data packets when polled by the cluster head. By introducing hierarchy, such a two-layered heterogeneous sensor network has better scalability than homogeneous sensor networks. It also has a smaller overall cost since networking functionalities are shifted from sensors to the cluster head. It also has a longer life time, as sensors send packets only when polled by the cluster head and less energy is consumed in collisions and idle listening. this type of network will be ideally suited for applications such as environmental monitoring. In this paper, we focus on finding energy efficient and collision-free polling schedules in the multi-hop cluster. To reduce energy consumption in idle listening, a schedule is optimal if it uses minimum time. We show that the problem of finding an optimal schedule is NP-hard, and then give a fast on-line algorithm. We also consider dividing a cluster into sectors to further reduce the idle listening time of sensors. We conducted simulations on the NS-2 simulator, and the results show that our polling scheme can reduce the active time of sensors by a significant amount while sustaining 100% throughput.

关键词： distributed computer systems

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Optimization of reconfiguration overhead by algorithmic transformations and hardware matching

Optimization of reconfiguration overhead by algorithmic tran...

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19th ieee international parallel and distributed processing symposium, IPDPS 2005

作者： Rullmann, Markus Siegel, Sebastian Merker, Renate Dresden University of Technology Circuits and Systems Laboratory 01062 Dresden Germany

ISBN: (纸本)0769523129

In this paper we present a method to optimize the over-head in dynamically reconfigurable computing systems. applications are considered to be partitioned into algorithmic blocks. Our method allows a reduction of overhead when reconfiguration between those blocks is required. For each block a variety of specifications is constructed using high level algorithmic transformations based on a partitioning method for nested loop programs. the partitioning method allows an efficient verification with the given design constraints. the specifications differ in resource usage and execution time. the reconfiguration costs are reduced by finding the best matching specifications of the algorithmic blocks. the specifications with the lowest reconfiguration cost are selected for implementation using the matching information as input for the implementation tools. Finally we present an optimal solution for a reconfigurable 2D mean filter. Two configurations with different filter sizes and word widths were implemented according to the matching specifications. We reduced the required logic area compared to the non-reconfigurable implementation and reduced significantly the reconfiguration costs.

关键词： parallel processing systems

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Monitoring and debugging parallel software with BCS-MPI on large-scale clusters

Monitoring and debugging parallel software with BCS-MPI on l...

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19th ieee international parallel and distributed processing symposium, IPDPS 2005

作者： Fernández, Juan Petrini, Fabrizio Frachtenberg, Eitan Departamento de Ingeniería y Tecnología de Computadores Universidad de Murcia 30071 Murcia Spain CCS-3 Modeling Algorithms and Informatics Los Alamos National Laboratory Los Alamos NM 87545 United States

ISBN: (纸本)0769523129

Buffered CoScheduled (BCS) MPI is a novel implementation of MPI based on global synchronization of all system activities. BCS-MPI imposes a model where all processes and their communication are tightly scheduled at a very fine granularity. thus, BCS-MPI provides a system that is much more controllable and deterministic. BCS-MPI leverages this regular behavior to provide a simple yet powerful monitoring and debugging subsystem that streamlines the analysis of parallel software. this subsystem, called Monitoring and Debugging System (MDS), provides exhaustive process and communication scheduling statistics. this paper covers in detail the design and implementation of the MDS subsystem, and demonstrates how the MDS can be used to monitor and debug not only parallel MPI applications but also the BCS-MPI runtime system itself. Additionally, we show that this functionality need not come at a significant performance loss.

关键词： Large scale systems

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Fault-tolerant parallel applications with dynamic parallel schedules

Fault-tolerant parallel applications with dynamic parallel s...

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19th ieee international parallel and distributed processing symposium, IPDPS 2005

作者： Gerlach, Sebastian Hersch, Roger D. School of Computer and Communication Sciences Switzerland

ISBN: (纸本)0769523129

Commodity computer clusters are often composed of hundreds of computing nodes. these generally off-the-shelf systems are not designed for high reliability. Node failures therefore drive the MTBF of such clusters to unacceptable levels. the software frameworks used for running parallel applications need to be fault-tolerant in order to ensure continued execution despite node failures. We propose an extension to the flow graph based Dynamic parallel Schedules (DPS) development framework that allows non-trivial parallel applications to pursue their execution despite node failures. the proposed fault-tolerance mechanism relies on a set of backup threads located in the volatile storage of alternate nodes. these backup threads are kept up to date by duplication of the transmitted data objects and periodical checkpointing of thread states. In case of a failure, the current state of the threads that were on the failed node is reconstructed on the backup threads by re-executing operations. the corresponding valid re-execution order is automatically deduced from the data flow graph of the DPS application. Multiple simultaneous failures can be tolerated, provided that for each thread either the active thread or its corresponding backup thread survives. For threads that do not store a local state, an optimized mechanism eliminates the need for duplicate data object transmissions. the overhead induced by the fault tolerance mechanism consists mainly of duplicate data object transmissions that can, for compute bound applications, be carried out in parallel with ongoing computations. the increase in execution time due to fault tolerance therefore remains relatively low. It depends on the communication to computation ratio and on the parallel program's efficiency.

关键词： Fault tolerant computer systems

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Dynamic scalable visualization for collaborative scientific applications

Dynamic scalable visualization for collaborative scientific ...

引用

19th ieee international parallel and distributed processing symposium, IPDPS 2005

作者： Li, Kai Hibbs, Matthew Wallace, Grant Troyanskaya, Olga Department of Computer Science Princeton University Princeton NJ 08544

ISBN: (纸本)0769523129

Science disciplines are experiencing a data avalanche. As a result, scientific research is limited by data analysis and visualization capabilities. We have been working closely with Genomic and Plasma Physics researchers on effective data visualization software tools. this paper reports our research on developing software tools for high-resolution display walls to alleviate the current limitation on visualization resolution and single-user window system. In the first case, we developed a novel data visualization tools for genomic data visualization that is dynamic and scale free. In the second case, we have developed a multi-cursor window system for shared data visualization for a collaborative environment. We have deployed both software tools to the scientific researchers. Our initial feedbacks show that these approaches have made significant impact on their productivity.

关键词： Computer supported cooperative work

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Efficient data access for parallel BLAST

Efficient data access for parallel BLAST

引用

19th ieee international parallel and distributed processing symposium, IPDPS 2005

作者： Lin, Heshan Ma, Xiaosong Chandramohan, Praveen Geist, Al Samatova, Nagiza Department of Computer Science North Carolina State University Computer Science and Mathematics Division Oak Ridge National Laboratory

ISBN: (纸本)0769523129

Searching biological sequence databases is one of the most routine tasks in computational biology. this task is significantly hampered by the exponential growth in sequence database sizes. Recent advances in parallelization of biological sequence search applications have enabled bioinformatics researchers to utilize high-performance computing platforms and, as a result, greatly reduce the execution time of their sequence database searches. However, existing parallel sequence search tools have been focusing mostly on parallelizing the sequence alignment engine. While the computation-intensive alignment tasks become cheaper with larger machines, data-intensive initial preparation and result merging tasks become more expensive. Inefficient handling of input and output data can easily create performance bottlenecks even on supercomputers. It also causes a considerable data management overhead. In this paper, we present a set of techniques for efficient and flexible data handling in parallel sequence search applications. We demonstrate our optimizations through improving mpiBLAST, an open-source parallel BLAST tool rapidly gaining popularity. these optimization techniques aim at enabling flexible database partitioning, reducing I/O by caching small auxiliary files and results, enabling parallel I/O on shared files, and performing scalable result processing protocols. As a result, we reduce mpiBLAST users' operational overhead by removing the requirement of prepartitioning databases. Meanwhile, our experiments show that these techniques can bring by an order of magnitude improvement to both the overall performance and scalability of mpiBLAST.

关键词： Data reduction

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Using manufacturing process flow for time synchronization in HLA-based simulation

Using manufacturing process flow for time synchronization in...

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9th ieee international symposium on distributed Simulation and Real-Time applications

作者： Gan, Boon Ping Low, Malcolm Yoke Hean Wang, Xiaoguang Turner, Stephen John D-SIMLAB Programme Singapore Institute of Manufacturing Technology 71 Nanyang Drive Singapore 638075 Singapore Parallel and Distributed Computing Centre School of Computer Engineering Nanyang Technological University Nanyang Avenue Singapore 639798 Singapore

Time synchronization has always been a critical deciding factor of whether interoperating simulation models using the High Level Architecture (HLA) is achievable efficiently. In this paper, we propose a conservative time synchronization algorithm that makes use of the manufacturing process flow information (a sequence of steps production lots flow through) in the computation of the request time. this time is used by the simulation federate to issue requests to advance time to the HLA Runtime Infrastructure (RTI). the proposed algorithm monitors the simulation events that potentially trigger external times tamp messages at the exit step and j processing steps before this exit step as well as simulation events that extend the timestamp of external messages. We evaluated the performance of this algorithm using a Borderless Fab simulation model on the AutoSched AP. the experimental results show that the algorithm performs much better than a straightforward use of the RTI's time synchronization, and the further back we went in looking at the processing steps, the better the execution time that was achieved. © 2005 ieee.

关键词： Computer architecture

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Strict priority versus weighted fair queueing in switched ethernet networks for time critical applications

Strict priority versus weighted fair queueing in switched et...

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19th ieee international parallel and distributed processing symposium, IPDPS 2005

作者： Georges, Jean-Philippe Divoux, thierry Rondeau, Eric Université Henri Poincaré Nancy Faculté des Sciences BP 239 F-54600 Vandœuvre Cedex France

ISBN: (纸本)0769523129

In an industrial or technical context, some of the communications are strongly time-constrained. Our objective is to evaluate the service offered by a switched Ethernet architecture. We have chosen the network calculus theory because it gives a good representation of the exchanges and enables to determine the maximum end to end delays. Previous models implementing a strict priority policy presented in [7] are improved in order to take into account the Weighted Fair Queueing mechanism which enables to balance the allocation of the network to the different traffics regarding the time contraints they have to respect. this paper also presents the new analytical formulas which upper bound the maximum end-to-end delays of the time-critical messages over the whole network. this enables to determine the optimal bandwith dedicated to both critical and best effort traffics. On an industrial scenario, Strict Priority and Weighted Fair Queue ing policies are finally compared.

关键词： Computer networks

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An experiment with high performance components for grid applications

An experiment with high performance components for grid appl...

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19th ieee international parallel and distributed processing symposium, IPDPS 2005

作者： Coppola, Massimo Pasquali, Marco Presti, Luigi Vanneschi, Marco via G. Moruzzi 1 56124 Pisa Italy Università di Pisa Dip. di Informatica Largo B. Pontecorvo 3 56127 Pisa Italy

ISBN: (纸本)0769523129

In this paper we describe an experiment in building Grid-aware software components as basic blocks for high-performance, adaptive Grid computations. Within the *** project we are working to the enhancement of the coordination language approach of the ASSIST parallel programming environment to support high-performance software components, that can react to the changes occurring on dynamic execution platforms. We are currently evaluating expressiveness and performance issues also by integrating ASSIST compilation tools with various component frameworks. In the paper we discuss results about a graphical application made up of four CCM components, each one produced by automatic encapsulation of a parallel program. We evaluate performance behaviour by comparing the composite application with the equivalent ASSIST one, on three different testbeds: homogeneous and heterogeneous clusters, and a small Grid over a WAN. We also report first results about an Application Manager component that applies a simple adaptive policy, reacting to pipeline unbalance, to vary the amount of employed computational resources.

关键词： Computer software

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MATLAB/simulink based hardware/software co-simulation for designing using FPGA configured soft processors

MATLAB/simulink based hardware/software co-simulation for de...

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19th ieee international parallel and distributed processing symposium, IPDPS 2005

作者： Ou, Jingzhao Prasanna, Viktor K. Department of Electrical Engineering University of Southern California Los Angeles CA 90089-2560 United States

ISBN: (纸本)0769523129

FPGA configured soft processors are an attractive choice for implementing many embedded systems. For application development using these soft processors, the users can execute portions of the applications as software programs and the other portions as customized hardware implementations. Being able to rapidly simulate various partitions of the applications on hardware and software is crucial to efficiently execute them on soft processors because (a) there are many possible configurations of soft processors, and (b) low-level simulation techniques are too time consuming for evaluating these different partitioning and configuration possibilities. While state-of-the-art design tools rely on low-level simulation and are unable to deliver such a fast simulation speed, we propose a high-level cycle-accurate hardware/software cosimulation environment based on MATLAB/Simulink for application development using soft processors. By utilizing the high-level cycle-accurate abstractions of the low-level hardware implementations and the arithmetic simulation capability provided by MATLAB/Simulink, our tool considerably accelerates the time for cycle-accurate functional simulation of both hardware and software portions of a given application running on soft processors. To illustrate our approach, we develop a CORDIC division application and a matrix multiplication application on a commercial soft processor. Up to 19.4x improvement in simulation time is achieved using our co-simulation environment compared with that of low-level simulation for various partitions of these applications and for various configurations of the soft processor.

关键词： parallel processing systems

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