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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

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SUPER: SUb-Graph parallelism for TransformERs 35

SUPER: SUb-Graph Parallelism for TransformERs

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Jain, Arpan Moon, Tim Benson, Tom Subramoni, Hari Jacobs, Sam Ade Panda, Dhabaleswar K. Van Essen, Brian Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA USA Lawrence Livermore Natl Lab Global Secur Comp Applicat Div Livermore CA USA

ISBN: (纸本)9781665440660

Transformer models have revolutionized the field of Natural Language processing (NLP) and they achieve state-of-the-art performance in applications like machine translation, question answering, regression, and summarization. However, training Transformers is challenging because of their large memory and compute requirements. the literature contains several approaches to parallelize training, like layer parallelism and pipeline parallelism, but they are optimized to benefit outof-core models and they don't exploit the inherent parallelism in Transformer models. Other work uses model parallelism to achieve weak scaling by increasing the model size. In this paper, we propose sub-graph parallelism that provides a significant performance improvement over pure data parallelism with a fixed number of resources, and as an additional technique for strong- and weak-scaling without increasing model capacity. Our technique accelerates the training of Transformer models and we generalize the concept to any neural network with multiple branches. We optimize the communication for sub-graph parallelism and combine it with data parallelism to scale performance up to 1024 GPUs. To decrease communication overheads, we propose a topology-aware scheme that limits inter-node communication. Finally, we empirically compare sub-graph parallelism with pure data parallelism and demonstrate its performance benefits in end-to-end training.

关键词： scalable deep learning transformers sub-graph parallelism algorithms deep learning distributed training

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Periodicity detection algorithm and applications on IoT data 20

Periodicity detection algorithm and applications on IoT data

引用

20th international symposium on parallel and distributed Computing (ISPDC)

作者： Tolas, Ramona Portase, Raluca Iosif, Andrei Potolea, Rodica Tech Univ Cluj Napoca Comp Sci Dept Cluj Napoca Romania

ISBN: (纸本)9781665432818

Data collected by sensors has hidden value that can be used to infer valuable knowledge about the system, such as identifying faults in transmission or functioning faults in various system components. Solutions for exploring and exploiting data need to be developed to extract such knowledge. this paper shows how the identification of transmission regularities can be used to extract knowledge about the overall system state. the focus of this work is defining a methodology for detecting transmission periodicity. In our approach, we evaluated other strategies, addressed various limitations they have, and narrowed their utility on real-world data. We further expand the scope by defining strategies for the identification of transmission gaps and duplicates. Finally, we validate the algorithms on samples of real industrial data obtained from monitoring different parts of home appliances.

关键词： Transmission pattern identification IoT data signal transmission periodicity real data processing

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A Streaming Accelerator for Heterogeneous CPU-FPGA processing of Graph applications

A Streaming Accelerator for Heterogeneous CPU-FPGA Processin...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： O'Brien, Francis Agostini, Matthew Abdelrahman, Tarek S. Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)9781665435772

We explore the heterogeneous acceleration of graph processing on a platform that tightly integrates an FPGA with a multicore CPU to share system memory in a cache-coherent manner. We design an accelerator for the scatter phase of scatter-gather vertex-centric iterative graph processing. the accelerator accesses graph data exclusively from system memory, sharing it at the cache line granularity with the CPU, thus enabling the concurrent use of both the accelerator and software threads. We implement and evaluate the accelerator on the second generation Intel Heterogeneous Architecture Research Platform (HARPv2). Our evaluation, using two key graph processing kernels and both synthetically-generated and real-world graphs, shows that: (1) our accelerator delivers a performance improvement of about 2.4X over a single CPU thread, (2) our concurrent use of software and hardware is efficient and delivers speedups over the use of just software threads or just the accelerator, and (3) heterogeneous hardware-software acceleration delivers high graph processing throughputs. these results demonstrate the viability and promise of combined CPU-FPGA processing in contrast to the traditional offload model that leaves the CPU idle during acceleration.

关键词： distributed processing Multicore processing Instruction sets Conferences Computer architecture throughput Software

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Shared-Memory Scalable k-Core Maintenance on Dynamic Graphs and Hypergraphs

Shared-Memory Scalable <i>k</i>-Core Maintenance on Dynamic ...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Gabert, Kasimir Pinar, Ali Catalyurek, Umit, V Georgia Inst Technol Atlanta GA 30332 USA Sandia Natl Labs Livermore CA USA

ISBN: (纸本)9781665435772

Computing k-cores on graphs is an important graph mining target as it provides an efficient means of identifying a graph's dense and cohesive regions. Computing k-cores on hypergraphs has seen recent interest, as many datasets naturally produce hypergraphs. Maintaining k-cores as the underlying data changes is important as graphs are large, growing, and continuously modified. In many practical applications, the graph updates are bursty, both with periods of significant activity and periods of relative calm. Existing maintenance algorithms fail to handle large bursts, and prior parallel approaches on both graphs and hypergraphs fail to scale as available cores increase. We address these problems by presenting two parallel and scalable fully-dynamic batch algorithms for maintaining k-cores on both graphs and hypergraphs. Both algorithms take advantage of the connection between k-cores and h-indices. One algorithm is well suited for large batches and the other for small. We provide the first algorithms that experimentally demonstrate scalability as the number of threads increase while sustaining high change rates in graphs and hypergraphs.

关键词： distributed processing Heuristic algorithms Scalability Conferences Maintenance engineering Approximation algorithms Pins

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Improving Availability and Scalability for RDMA Load Balancing with In-network Reordering

Improving Availability and Scalability for RDMA Load Balanci...

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international symposium on parallel and distributed processing with applications, ISPA

作者： Jinbin Hu Ruiqian Li Shuying Rao Jin Wang Changsha University of Science and Technology Changsha China Hunan University of Science and Technology Xiangtan China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

Remote Direct Memory Access (RDMA) is widely deployed in datacenter networks (DCNs) due to its ultra-low latency, high throughput, and low CPU overhead. Since RDMA is sensitive to out-of-order packets, the previous load balancing schemes designed based on TCP do not work well in RDMA networks. Recently proposed load balancing schemes focus on solving packet reordering within the network. However, the existing solutions cannot be extended in practice because the required queues far exceed common switch capabilities. In this paper, we propose a scalable and efficient load balancing called SELB to improve availability and scalability. SELB employs a clustering algorithm to categorize equal-cost paths and then reroutes traffic to the same cluster parallel paths to reduce the degree of out-of-order and improve queue utilization. the NS-3 simulation results demonstrate that SELB reduces the average flow completion time (FCT) and the 99th percentile FCT by up to 33% and 21%, respectively, compared to the state-of-the-art load balancing schemes.

关键词： Out of order distributed processing Scalability Simulation Clustering algorithms Switches Load management throughput Classification algorithms

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ARBALEST: Dynamic Detection of Data Mapping Issues in Heterogeneous OpenMP applications 35

ARBALEST: Dynamic Detection of Data Mapping Issues in Hetero...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Yu, Lechen Protze, Joachim Hernandez, Oscar Sarkar, Vivek Georgia Inst Technol Coll Comp Atlanta GA 30332 USA Rhein Westfal TH Aachen IT Ctr Aachen Germany Oak Ridge Natl Lab Comp Sci Res Oak Ridge TN USA

ISBN: (纸本)9781665440660

From OpenMP 4.0 onwards, programmers can off-load code regions to accelerators by using the target offloading feature. However, incorrect usage of target offloading constructs may incur data mapping issues. A data mapping issue occurs when the host fails to observe updates on the accelerator or vice versa. It may further lead to multiple memory issues such as use of uninitialized memory, use of stale data, and data race. To the best of our knowledge, currently there is no prior work on dynamic detection of data mapping issues in heterogeneous OpenMP applications. In this paper, we identify possible root causes of data mapping issues in OpenMP's standard memory model and the unified memory model. We find that data mapping issues primarily result from incorrect settings of map and nowait clauses in target offloading constructs. Further, the novel unified memory model introduced in OpenMP 5.0 cannot avoid the occurrence of data mapping issues. To mitigate the difficulty of detecting data mapping issues, we propose ARBALEST, an on-the-fly data mapping issue detector for OpenMP applications. For each variable mapped to the accelerator, ARBALEST's detection algorithm leverages a state machine to track the last write's visibility. ARBALEST requires constant storage space for each memory location and takes amortized constant time per memory access. To demonstrate ARBALEST's effectiveness, an experimental comparison with four other dynamic analysis tools (Valgrind, Archer, AddressSanitizer, MemorySanitizer) has been carried out on a number of open-source benchmark suites. the evaluation results show that ARBALEST delivers demonstrably better precision than the other four tools, and its execution lime overhead is comparable to that of state-of-the-art dynamic analysis tools.

关键词： Dynamic Analysis Concurrency Bug Detection Data Mapping Issue OpenMP Accelerator

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MultiLogVC: Efficient Out-of-Core Graph processing Framework for Flash Storage 35

MultiLogVC: Efficient Out-of-Core Graph Processing Framework...

引用

35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Matam, Kiran Kumar Hashemi, Hanieh Annavaram, Murali Facebook Inc Menlo Pk CA 94025 USA Univ Southern Calif Elect Engn Dept Los Angeles CA 90007 USA

ISBN: (纸本)9781665440660

Graph analytics are at the heart of a broad range of applications such as drug discovery, page ranking, transportation systems, and recommendation models. When graph size exceeds the available memory size in a computing node, out-of-core graph processing is needed. For the widely used out-of-core graph processing systems. the graphs are stored and accessed from a long latency SSD storage, which becomes a significant performance bottleneck. To tackle this long latency this work exploits the key insight that that nearly all graph algorithms have a dynamically varying number of active vertices that must be processed in each iteration. However, existing graph processing frameworks, such as GraphChi, load the entire graph in each iteration even if a small fraction of the graph is active. this limitation is due to the structure of the graph storage used by these systems. In this work, we propose to use a compressed sparse row (CSR) based graph storage that is more amenable for selectively loading only a few active vertices in each iteration. However, CSR based graph processing suffers from random update propagation to many target vertices. To solve this challenge, we propose to use a multi-log update mechanism that logs updates separately, rather than directly update the active edges and vertices in a graph. the multi-log system maintains a separate log per each vertex interval (a group of vertices). this separation enables efficient processing of all updates bound to each vertex interval by just loading the corresponding log. Further, by logging all the updates associated with a vertex interval in one contiguous log this approach reduces read amplification since all the pages in the log will be processed in the next iteration without wasted page reads. Over the current state of the art out-of-core graph processing framework, our evaluation results show that the MultiLogVC framework improves performance by up to 17.84x, 1.19x, 1.65x, 1.38x, 3.15x, and 6.00x for the widely

关键词： out-of-core graph processing graph analytics SSD storage systems log storage

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Exploring MPI Collective I/O and File-per-process I/O for Checkpointing a Logical Inference Task

Exploring MPI Collective I/O and File-per-process I/O for Ch...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Fan, Ke Micinski, Kristopher Gilray, thomas Kumar, Sidharth Univ Alabama Birmingham Birmingham AL 35294 USA Syracuse Univ Syracuse NY 13244 USA

ISBN: (纸本)9781665435772

We present a scalable parallel I/O system for a logical-inferencing application built atop a deductive database. Deductive databases can make logical deductions (i.e. conclude additional facts), based on a set of program rules, derived from facts already in the database. Datalog is a language or family of languages commonly used to specify rules and queries for a deductive database. applications built using Datalog can range from graph mining (such as computing transitive closure or k-cliques) to program analysis (control and data-flow analysis). In our previous papers, we presented the first implementation of a data-parallel Datalog built using MPI. In this paper, we present a parallel I/O system used to checkpoint and restart applications built on top of our Datalog system. State of the art Datalog implementations, such as Souffle, only support serial I/O, mainly because the implementation itself does not support many-node parallel execution. Computing the transitive closure of a graph is one of the simplest logical-inferencing applications built using Datalog;we use it as a micro-benchmark to demonstrate the efficacy of our parallel I/O system. Internally, we use a nested B-tree data-structure to facilitate fast and efficient in-memory access to relational data. Our I/O system therefore involves two steps, converting the application data-layout (a nested B-tree) to a stream of bytes followed by the actual parallel I/O. We explore two popular I/O techniques POSIX I/O and MPI collective I/O. For extracting performance out of MPI Collective I/O we use adaptive striping, and for POSIX I/O we use file-per-process I/O. We demonstrate the scalability of our system at up to 4,096 processes on the theta supercomputer at the Argonne National Laboratory.

关键词： Checkpointing distributed processing Scalability Conferences Supercomputers Deductive databases Task analysis

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Revisiting Huffman Coding: Toward Extreme Performance on Modern GPU Architectures 35

Revisiting Huffman Coding: Toward Extreme Performance on Mod...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Tian, Jiannan Rivera, Cody Di, Sheng Chen, Jieyang Liang, Xin Tao, Dingwen Cappello, Franck Washington State Univ Sch Elect Engn & Comp Sci Pullman WA 99164 USA Univ Alabama Dept Comp Sci Tuscaloosa AL 35487 USA Argonne Natl Lab Math & Comp Sci Div Lemont IL USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Illinois Champaign IL USA

ISBN: (纸本)9781665440660

Today's high-performance computing (HPC) applications are producing vast volumes of data, which are challenging to store and transfer efficiently during the execution, such that data compression is becoming a critical technique to mitigate the storage burden and data movement cost. Huffman coding is arguably the most efficient Entropy coding algorithm in information theory, such that it could be found as a fundamental step in many modern compression algorithms such as DEFLATE. On the other hand, today's HPC applications are more and more relying on the accelerators such as GPU on supercomputers, while Huffman encoding suffers from low throughput on GPUs, resulting in a significant bottleneck in the entire data processing. In this paper, we propose and implement an efficient Huffman encoding approach based on modern GPU architectures, which addresses two key challenges: (1) how to parallelize the entire Huffman encoding algorithm, including codebook construction, and (2) how to fully utilize the high memory-bandwidth feature of modern GPU architectures. the detailed contribution is fourfold. (1) We develop an efficient parallel codebook construction on GPUs that scales effectively with the number of input symbols. (2) We propose a novel reduction based encoding scheme that can efficiently merge the codewords on GPUs. (3) We optimize the overall GPU performance by leveraging the state-of-the-art CUDA APIs such as Cooperative Groups. (4) We evaluate our Huffman encoder thoroughly using six real-world application datasets on two advanced GPUs and compare with our implemented multi-threaded Huffman encoder. Experiments show that our solution can improve the encoding throughput by up to 5.0x and 6.8x on NVIDIA RTX 5000 and V100, respectively, over the state-of-the-art GPU Huffman encoder, and by up to 3.3x over the multi-thread encoder on two 28-core Xeon Platinum 8280 CPUs.

关键词： distributed processing Platinum Graphics processing units Computer architecture throughput Data processing Supercomputers

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Jigsaw: A Slice-and-Dice Approach to Non-uniform FFT Acceleration for MRI Image Reconstruction 35

Jigsaw: A Slice-and-Dice Approach to Non-uniform FFT Acceler...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： West, Brendan L. Fessler, Jeffrey A. Wenisch, thomas F. Univ Michigan Ann Arbor MI 48109 USA

ISBN: (纸本)9781665440660

the Fast Fourier Transform (FFT) is a fundamental algorithm in signal processing;significant efforts have been made to improve its performance using software optimizations and specialized hardware accelerators. Computational imaging modalities, such as MRI, often rely on the Non-uniform Fast Fourier Transform (NuFFT), a variant ()I' the EFT for processing data acquired from non-uniform sampling patterns. the most time-consuming step of the NuFFT algorithm is "gridding," wherein non-uniform samples are interpolated to allow a uniform FFT to be computed over the data. Each non-uniform sample affects a window of non-contiguous memory locations, resulting in poor cache and memory bandwidth utilization. As a result, gridding can account for more than 99.6% of the NuFFT computation time, while the FFT requires less than 0.4%. We present Slice-and-Dice, a novel approach to the NuFFT's gridding step that eliminates the presorting operations required by prior methods and maps more efficiently to hardware. Our GPI! implementation achieves gridding speedups of over 250x and 16x vs prior ***-art CPU and GPU implementations, respectively. We achieve further speedup and energy efficiency gains by implementing Slice-and-Dice in hardware with JIGSAW, a streaming hardware accelerator for non-uniform data gridding. JIGSAW uses stall-free fixed-point pipelines to process M non-uniform samples in approximately M cycles, irrespective of sampling pattern-yielding speedups of over 1500x the CPU baseline and 36x the state-of-the-art GPU implementation, consuming similar to 200 mW power and similar to 12 mm(2) area in 16 nm technology. Slice-and-Dice GPU and JIGSAW ASIC implementations achieve unprecedented end-to-end NuFFT speedups of 8x and 36x compared to the state-of-the-art GPU implementation, respectively.

关键词： Runtime Power demand Fast Fourier transforms Magnetic resonance imaging Software algorithms Graphics processing units Signal processing algorithms

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