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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

共 2574 条记录，以下是2001-2010 订阅

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A multiple associative model to support branches in data parallel applications using the manager-worker paradigm

A multiple associative model to support branches in data par...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： W. Chantamas J.W. Baker Department of Computer Science Kent University Kent OH USA

ASC (associative computing model) and MASC (multiple associative computing model) have long been studied in the Department of Computer Science at Kent State University. While the previous studies provide the background and the basic definition of the model, the description of the interactions between the instruction streams (ISs) is very brief, high level, and incomplete. One change here is that we specify the interaction between ISs and consider that all of the ISs operate on the same clock in order to support predictable worst case computation times, while earlier the ISs were assumed to interact in a MIMD type fashion. this paper provides a detailed explanation as to how these interactions can be supported in the case where only a few ISs are supported.

关键词： Concurrent computing Broadcasting Application software Computer science Computer aided instruction Identity management systems Telephony Clocks Computational modeling parallel processing

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A versatile, proactive dependability approach to handling unanticipated events in distributed systems

A versatile, proactive dependability approach to handling un...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： Priya Narasimhan Raj Rajkumar Gautam thaker P. Lardieri Carnegie Mellon University Pittsburgh PA USA Lockheed Martin ATL Cherry Hill NJ USA

the MEAD system that we are developing employs a synergistic combination of a reactive and a proactive fault-tolerance approach in order to address unanticipated events and hazards in real-time, fault-tolerant distributed systems. the reactive fault-tolerance approach involves active monitoring of the system to adapt the provided QoS and to allocate resources based on current conditions in the system. the proactive approach involves monitoring both the distributed applications and the network to seek pre-cursors to imminent failures, and then to trigger fault-recovery mechanisms in advance of the occurrence of the failure. the underlying ideas of the MEAD system have demonstrated initial promise through our enhanced capabilities to handle failures and unanticipated events, and to reduce jitter under faulty conditions.

关键词： Fault tolerant systems Surges Hazards Real time systems Condition monitoring Resource management Event detection Creep Programming profession Jitter

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A fixed-structure learning automaton solution to the stochastic static mapping problem

A fixed-structure learning automaton solution to the stochas...

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international symposium on parallel and distributed processing (IPDPS)

作者： G. Horn B.J. Oommen SIMULA Research Laboratory Lysaker Norway School of Computer Science Carleton University Ottawa ONT Canada

this paper considers the problem of distributing the processes of a parallel application onto a set of computing nodes. this problem called the static mapping problem (SMP) is known to be NP-hard, and has been tackled using heuristic solutions. the objective of this paper is to present the first reported learning automaton (LA) based solution to the SMP, generated by the close resemblance of the SMP to the equipartitioning problem. the LA in question is of the so-called fixed-structure family, solution to the equipartitioning problem is then modified to solve the SMP. Several algorithmic variants of this solution have been implemented, and these have all been rigorously tested and evaluated through extensive simulations on randomly generated parallel applications. the focus in this work is to demonstrate the applicability of LA to the SMP, not to optimise and evaluate the performance of the proposed strategy. the results presented here clearly demonstrate that LA provides a promising tool that can effectively solve the mapping problem.

关键词： Learning automata Stochastic processes Application software Concurrent computing distributed computing Testing parallel processing Bandwidth Processor scheduling Laboratories

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A model-driven performance analysis framework for distributed, performance-sensitive software systems

A model-driven performance analysis framework for distribute...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： S.S. Gokhale Aniruddha Gokhale J. Gray Department of Computer Science and Engineering University of Connecticut Storrs CT USA Department of Electrical Engineering and Computer Science Vanderbilt University Nashville TN USA Department of Computer and Information Science University of Alabama Birmingham Birmingham AL USA

Large-scale, distributed, performance-sensitive software (DPSS) systems from the basis of mission- and often safety-critical applications. DPSS systems comprise of many independent artifacts, such as network/bus interconnects, many coordinated local and remote endsystems, and multiple layers of software. DPSS systems demand multiple, simultaneous predictable performance requirements such as end-to-end latencies, throughput, reliability and security, while also requiring the ability to control and adapt operating characteristics for applications with respect to such features as time, quantity of information, and quality of service (QoS) properties including predictability, controllability, and adaptability of operating characteristics for applications with respect to such features as time, quantity of information, accuracy, confidence and synchronization. All these issues become highly volatile in large-scale DPSS systems due to the dynamic interplay of the many interconnected parts that are often constructed from smaller parts.

关键词： Performance analysis Software systems Large-scale systems Application software Quality of service Software performance Software safety Delay throughput Information security

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A low-power and domain-specific reconfigurable FFT fabric for system-on-chip applications

A low-power and domain-specific reconfigurable FFT fabric fo...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： Y. Zhao A.T. Erdogan T. Arslan School of Engineering and Electronics University of Edinburgh Edinburgh UK Institute for System Level Integration Livingston UK

A low-power dynamic reconfigurable FFT fabric is proposed in this paper. the architecture is served as a scalable IP core, which is suitable for system on chip applications. the system can be configured as 16, 32, 64, 128, 256, 512 and 1024-point FFT. Compared with a conventional ASIC FFT processor, this FFT fabric is characterized by having dynamic reconfigurability while incurring only a 12 /spl sim/ 19% increase in energy consumption, and requiring 14% more area than a 1024-point non-reconfigurable FFT fabric. On the other hand, compared with a FFT processor which is mapped onto a general purpose reconfigurable architecture, it has 30 /spl sim/ 94% less energy consumption.

关键词： Fabrics System-on-a-chip Switches Energy consumption Digital signal processing Hardware Field programmable gate arrays Signal processing algorithms Application specific integrated circuits Reconfigurable architectures

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Scenario-oriented design for single chip heterogeneous multiprocessors

Scenario-oriented design for single chip heterogeneous multi...

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international symposium on parallel and distributed processing (IPDPS)

作者： J.A.M. Paul Electrical and Computer Engineering Department Carnegie Mellon University Pittsburgh PA USA

the design of next generation single chip computers may require the selection, programming and coordination of tens to hundreds of individual processing elements (PEs) of several or tens of heterogeneous types. this paper outlines differences in the design process for these next generation single chip systems from that of traditional designs. then it focuses on a novel design strategy, scenario-oriented design (SOD). SOD is just one design strategy that arises because of the potential of considering applications, schedulers, and hardware as they interact to form a system instead of viewing them as separate design domains. By leveraging one against the other, the system and its design process can be optimized in new ways. this is made possible by reducing the modeling detail of each design domain within a system in high level simulation.

关键词： Hardware Prognostics and health management System-on-a-chip Delay Network-on-a-chip Application specific integrated circuits Bandwidth Concurrent computing distributed computing USA Councils

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A cordic-based processor extension for scalar and vector processing

A cordic-based processor extension for scalar and vector pro...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： R. Farivar M. Fazeli H. Sarbazi-Azad Department of Computer Engineering Sharif University of Technology Tehran Iran IPM School of Computer Science & Department of Computer Engineering Sharif University of Technology Tehran Iran

Trigonometric calculations play a significant role in scientific and multimedia applications. Such applications usually use vectors of data, thus it is essential to use SIMD-based computing for them. State of the art processors such as Pentium family processors have SIMD capabilities, MMX, SSE and SSE2 to name a few. But these extensions usually come short of performing trigonometric functions calculation. this paper presents a CORDIC-based vector processor extension to accelerate trigonometric calculations. the suggested architecture works with a vector of data, as well as scalar data. this architecture has been synthesized both for FPGA and ASIC and the results have shown a significant improvement in throughput over conventional processors.

关键词： Computer architecture Application software Field programmable gate arrays Application specific integrated circuits Discrete Fourier transforms throughput Hardware Fourier transforms Coprocessors Educational institutions

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distributed storage layout schemes

Distributed storage layout schemes

引用

international symposium on parallel and distributed processing (IPDPS)

作者： P. Sobe Institute of Computer Engineering University of Lübeck Germany

When distributing data across several nodes, two different approaches exist. the first one consists in distribution of the data object itself e.g. in striping. the second approach is aggregation of local storages, whereby each data object is assigned to a home storage node. From the viewpoint of fault-tolerant data layouts, these schemes seem to be similar. In both cases the addition of parity, e.g. RAID level 3, level 5 or Reed-Solomon codes provide tolerance against node failures. A closer look shows differences in reachable access rates, needed number of messages and recovery cost. In this paper we compare both approaches and provide a method for self-reconfiguration. the transformation from a parity grouping layout to a striping layout is shown to be feasible for stepwise and concurrent operation during data access.

关键词： Fault tolerance Checkpointing Costs File systems Bandwidth distributed computing Data engineering Reed-Solomon codes Application software Computer applications

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A quality-of-service architecture for future grid computing applications

A quality-of-service architecture for future grid computing ...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： L.-O. Burchard B. Linnert F. Heine M. Hovestadt O. Kao A. Keller Faculty of Computer Science and Electrical Engineering Technische Universität Berlin Germany Paderborn Center for Parallel Computing (PC2) Universität Paderborn Germany

the next generation grid applications demand grid middleware for a flexible negotiation mechanism supporting various ways of quality-of-service (QoS) guarantees. In this context, a QoS guarantee covers simultaneous allocations of various kinds of different resources, such as processor runtime, storage capacity, or network bandwidth, which are specified in the form of service level agreements (SLA). Currently, a gap exists between the capabilities of grid middleware and the underlying resource management systems concerning their support for QoS and SLA negotiation. In this paper we present an approach which closes this gap. Introducing the architecture of the virtual resource manager, we highlight its main QoS management features like run-time responsibility, co-allocation, and fault tolerance.

关键词： Quality of service Computer architecture Grid computing Middleware Resource management Application software Context-aware services Runtime Bandwidth Usability

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Accelerating scientific applications with the SRC-6 reconfigurable computer: methodologies and analysis

Accelerating scientific applications with the SRC-6 reconfig...

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international symposium on parallel and distributed processing (IPDPS)

作者： M.C. Smith J.S. Vetter X. Liang Oak Ridge National Laboratory Oak Ridge TN USA Department of Computer Science Jackson State University USA

Reconfigurable computing offers the promise of performing computations in hardware to increase performance and efficiency while retaining much of the flexibility of a software solution. Recently, the capacities of reconfigurable computing devices, like field programmable gate arrays, have risen to levels that make it possible to execute 64b floating-point operations. SRC Computers has designed the SRC-6 MAPstation to blend the benefits of commodity processors with the benefits of reconfigurable computing. In this paper, we describe our effort to accelerate the performance of several scientific applications on the SRC-6. We describe our methodology, analysis, and results. Our early evaluation demonstrates that the SRC-6 provides a unique software stack that is applicable to many scientific solutions and our experiments reveal the performance benefits of the system.

关键词： Acceleration Application software Hardware Field programmable gate arrays Microprocessors Signal processing algorithms Software performance Computer architecture Performance analysis Laboratories

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