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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

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Quantization improvements for LU Decomposition to Solve Linear Equations 19

Quantization improvements for LU Decomposition to Solve Line...

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19th ieee international symposium on parallel and distributed processing with applications (ieee ISPA)

作者： Chen, Lin He, Kang Jiang, Hao Barrio, Roberto Liu, Jie Li, Tiejun Natl Univ Def Technol Sci & Technol Parallel & Distributed Proc Lab Lab Software Engn Complex Syst Changsha Peoples R China Natl Univ Def Technol Coll Comp Sci & Technol Changsha Peoples R China Univ Zaragoza Dept Appl Math E-50009 Zaragoza Spain

ISBN: (纸本)9781665435741

Quantization is an effective method for compressing Deep Neural Networks. Now, it is considered to accelerate the traditional HPC applications. In this article, we present a quantization method (q8gemm) using integer 8-bits(INT8) for matrix multiplication, which is implemented by block techniques to overcome the overflow problem. We choose different scales for one matrix's each row and those for the other matrix's each column to keep the numbers in range. With the intel advanced matrix extension cblas_gemm_s8u8s32, our q8gemm can accelerate panel-matrix multiplication in LU factorization. Furthermore, we propose a new mixed-precision solver (q8gesv(1)) for the linear equations. Using q8gemm in INT8, q8gesv modifies LU factorization in FP32 and then utilizes GMRES iterative refinement in FP 64 to bring the solution back to 64 bits accuracy. Numerical tests show that on two Intel CPU platforms with avx2 and avx512, q8gemm achieves a speedup of 1.313-1.621 over cblas_sgemm of MKL. the execution time of cblas_gemm_s8u8s32 makes up 86.78%-0.85% of the q8gemm. By means of q8gemm, our q8gesv can achieve a speedup of 1.176-1.493 over the optimized Higham's mixed-precision algorithm utilized in the HPL-AI benchmark and a speedup of 1.1-1.459 over the LAPACKE_dsgesv function from MKL LAPACK. Meanwhile, q8gesv runs up to 2.859X faster on Intel(R) Core(TM) i5-10600KF and to 2.224X faster on Intel(R) Xeon(R) Gold 6130 than the LAPACKE_dgesv function from MKL LAPACK.

关键词： GMRES-IR LU Factorization Matrix Multiplication Mixed-precision Quantization

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Scalable Performance Prediction of Irregular Workloads in Multi-Phase Particle-in-Cell applications

Scalable Performance Prediction of Irregular Workloads in Mu...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Chenna, Sai P. Lam, Herman Stitt, Greg Balachandar, S. Univ Florida Elect & Comp Engn Gainesville FL 32611 USA Univ Florida Mech & Aerosp Engn Gainesville FL USA

ISBN: (纸本)9781665435772

the demand for reliable performance prediction of large-scale systems is ever-increasing. With the constant need of application users for faster execution and the expectation on system administrators to efficiently allocate system resources, reliable performance prediction frameworks are crucial for identifying scalability bottlenecks which result in suboptimal performance and poor resource utilization. Such challenges in scalable performance prediction are further exacerbated by irregular applications which present dynamic workload fluctuations across processors. In this paper, we propose a novel trace-driven performance prediction framework to reliably predict the performance of a class of irregular applications that employs the Particle-in-Cell (PIC) method. the framework provides multiple advantages in terms of scalability prediction, algorithm evaluation, and performance tuning. To demonstrate scalability prediction, we predicted the performance of CMT-nek, a large-scale scientific application which employs the PIC method, on Quartz (a DOE HPC system) with an average Mean Absolute Percentage Error (MAPE) of 8.42%. For algorithm evaluation, we evaluated the efficiency of two candidate particle mapping algorithms used in CMT-nek. For performance tuning, we performed a parameter study to assess the impact of a key problem parameter in CMT-nek on application performance.

关键词： performance modeling irregular workloads trace-based simulation particle-in-cell load-balancing

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MultiGrid on FPGA Using Data parallel C++ 36

MultiGrid on FPGA Using Data Parallel C++

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36th ieee international parallel and distributed processing symposium Workshops, IPDPSW 2022

作者： Siefert, Christopher Olivier, Stephen L. Voskuilen, Gwendolyn Young, Jeffrey Sandia National Laboratories AlbuquerqueNM United States Georgia Institute of Technology AtlantaGA United States

ISBN: (纸本)9781665497473

Centered on modern C++ and the SYCL standard for heterogeneous programming, Data parallel C++ (dpc++) and Intel's oneAPI software ecosystem aim to lower the barrier to entry for the use of accelerators like FPGAs in diverse applications. In this work, we consider the usage of FPGAs for scientific computing, in particular with a multigrid solver, MueLu. We report on early experiences implementing kernels of the solver in DPC++ for execution on Stratix 10 FPGAs, and we evaluate several algorithmic design and implementation choices. these choices not only impact performance, but also shed light on the capabilities and limitations of DPC++ and oneAPI. © 2022 ieee.

关键词： Field programmable gate arrays (FPGA)

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A parallel Meta-Solver for the Multi-Objective Set Covering Problem

A Parallel Meta-Solver for the Multi-Objective Set Covering ...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Marshall, Ryan J. Weerasena, Lakmali Skjellum, Anthony Univ Tennessee UTC SimCtr Chattanooga TN 37996 USA Univ Tennessee Dept Math Chattanooga TN USA

ISBN: (纸本)9781665435772

the multi-objective set covering problem (MOSCP) appears in many different real-world applications. We implemented a meta-solver in C++ that introduces shared-memory concurrency using OpenMP. It incorporates a commonly used Mixed Integer Problem (MIP) solver to find initial solutions with a linear programming (LP) solver that enumerates possible solutions over a tree of subproblems using a local branch approach. Adhering to a finite cutoff value, solutions are ordered as they are passed back up the tree to produce the set of Pareto fronts. In this paper, we present a serial version of the meta-solver with a novel search procedure that outperforms a previous implementation, and when parallelization techniques are applied, a 9-12x speedup is achieved with the possibility of further improvement for large problems.

关键词： Multi-objective parallel computing Algorithm Approximation Set Cover

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Improving the MPI-IO Performance of applications with Genetic Algorithm based Auto-tuning

Improving the MPI-IO Performance of Applications with Geneti...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Bagbaba, Ayse Wang, Xuan Univ Stuttgart High Performance Comp Ctr Stuttgart HLRS Stuttgart Germany

ISBN: (纸本)9781665435772

parallel I/O is an essential part of scientific applications running on high-performance computing systems. Understanding an application's parallel I/O behavior and identifying sources of performance bottlenecks require a multi-layer view of the I/O. Typical parallel I/O stack layers offer many tunable parameters that can achieve the best possible I/O performance. However, scientific users do often not have the time nor the experience for investigating the proper combination of these parameters for each application use-case. Auto-tuning can help users by automatically tuning I/O parameters at various layers transparently. In auto-tuning, using naive strategy, running an application by trying all possible combinations of tunable parameters for all layers of the I/O stack to find the best settings is an exhaustive search through the huge parameter space. this strategy is infeasible because of the long execution times of trial runs. In this paper, we propose a genetic algorithm-based parallel I/O auto-tuning approach that can hide the complexity of the I/O stack from users and auto-tune a set of parameter values for an application on a given system to improve the I/O performance. In particular, our approach tests a set of parameters and then, modifies the combination of these parameters for further testing based on the I/O performance. We have validated our model using two I/O benchmarks, namely IOR and MPI-Tile-IO. We achieved an increase in I/O bandwidth of up to 7.74xover the default parameters for IOR and 5.59xover the default parameters for MPI-Tile-IO.

关键词： parallel I/O Auto-tuning Genetic Algorithm MPI-IO Lustre

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Autonomous Load Balancing in distributed Hash Tables Using Churn and the Sybil Attack

Autonomous Load Balancing in Distributed Hash Tables Using C...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Rosen, Andrew Levin, Benjamin Bourgeois, Anu G. Temple Univ Dept Comp Sci Philadelphia PA 19122 USA Georgia State Univ Dept Comp Sci Atlanta GA 30303 USA

ISBN: (纸本)9781665435772

distributed Hash Tables (DHTs) are an integral foundation for a variety of modern internet applications. In previous work, we have shown that DHTs can also be used as a means of organizing a large number of workers to tackle large-scale computing problems in a fault tolerant context. Whether a DHT is being used for file access or distributing a large-scale computing job, a cryptographic hash function is used to assign keys for nodes and data. Ideally, these would be uniformly distributed across the available range, thus evenly distributing the nodes and tasks. However, this is rarely the case in practice and as a result, the workload can become highly unbalanced. To address this issue, there have been numerous methods proposed for load balancing DHTs, but often they are a centralized approach. In this paper, we present four methods to autonomously balance the load of DHTs: 1) induced churn;2) random injection of Sybil Nodes;3) neighbor injection;and 4) invitation of nodes with low workloads. Each approach is completely decentralized, requiring minimal overhead, with individual nodes making decisions based only upon local information. What makes our approach unique is that the strategies rely on using the inherent churn in a DHT or by a variation of the Sybil attack to balance the workload. We simulate the four strategies on a Chord DHT and show they significantly rebalance the workload in a DHT. the strategy of randomly injecting virtual "Sybil" nodes performed the best in terms of balance and speedup.

关键词： distributed Computing Decentralized Systems Peer-to-Peer Networks distributed Hash Tables Self-Organizing Networks Load-Balancing Sybil Attack

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Beyond Fork-Join: Integration of Performance Portable Kokkos Kernels with HPX

Beyond Fork-Join: Integration of Performance Portable Kokkos...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Daiss, Gregor Simberg, Mikael Reverdell, Auriane Biddiscombe, John Pollinger, theresa Kaiser, Hartmut Pfluger, Dirk Univ Stuttgart Inst Parallel & Distributed Syst Sci Comp Stuttgart Germany Swiss Natl Supercomp Ctr Porza Switzerland Louisiana State Univ CCT Baton Rouge LA 70803 USA

ISBN: (纸本)9781665435772

Between a widening range of GPU vendors and the trend of having more GPUs per compute node in supercomputers such as Summit, Perlmutter, Frontier and Aurora, developing performant yet portable distributed HPC applications becomes ever more challenging. Leveraging existing solutions like Kokkos for platform-independent code and HPX for distributing the application in a task-based fashion can alleviate these challenges. However, using such frameworks in the same application requires them to work together seamlessly. In this work we present an HPX Kokkos integration that works both ways: we can integrate CPU and GPU Kokkos kernels as HPX tasks and inversely use HPX worker threads to work on Kokkos kernels. Using HPX futures makes launching and synchronizing Kokkos kernels from multiple threads easy, allowing us to move away from the more traditional fork-join model. To evaluate our integrations we ported existing Vc and CUDA kernels within an existing HPX application, Octo-Tiger, to use Kokkos instead. We achieve comparable, or better, performance than with previous Vc and CUDA kernels, showing both the viability of our HPX Kokkos integration, as well as future-proofing Octo-Tiger for a wider range of potential machines. Furthermore, we introduce event polling for synchronizing CUDA kernels (or Kokkos kernels on the respective backend) achieving speedups over the previous solution using callbacks.

关键词： Performance Portability Task-based Programming Kokkos HPX SIMD GPU CUDA

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Efficient Heuristic Algorithm to Speed up GraphCut in GPU for Image Stitching

Efficient Heuristic Algorithm to Speed up GraphCut in GPU fo...

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international symposium on parallel Architectures, Algorithms and Programming (PAAP)

作者： Tai Nguyen Minh Bui Huong Ninh Tu Nguyen Hai Tien Tran Viettel Aerospace Institute Viettel Group

ISBN: (纸本)9781665452199

GraphCut algorithm has been widely utilized to solve various types of computer vision problems. Its expensive computational cost encouraged many researchers to improve the speed of the algorithm. Recent works proposed schemes that work on parallel computing platforms such as CUDA. However, the problem of low convergence speed prevents the usage of GraphCut for real time applications. In this paper, we propose global suppression heuristic to boost the convergence process of the algorithm. A parallel implementation of GraphCut algorithm on CUDA designed for the image stitching problem is introduced. Our method achieves up to 3× time boost on the graph of size 80×480 compared to the best sequential GraphCut algorithm while achieving satisfactory stitched images, suitable for panorama applications. Our source code will be soon available for further research.

关键词： Computer vision Heuristic algorithms Source coding Graphics processing units Programming parallel processing Real-time systems

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Fast HBM Access with FPGAs: Analysis, Architectures, and applications

Fast HBM Access with FPGAs: Analysis, Architectures, and App...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Holzinger, Philipp Reiser, Daniel Hahn, Tobias Reichenbach, Marc Friedrich Alexander Univ Erlangen Nurnberg FAU Chair Comp Architecture Dept Comp Sci Erlangen Germany

ISBN: (纸本)9781665435772

Over the past few decades, the gap between rapidly increasing computational power and almost stagnating memory bandwidth has steadily worsened. Recently, 3D die-stacking in form of High Bandwidth Memory (HBM) enabled the first major jump in external memory throughput in years. In contrast to traditional DRAM it compensates its lower clock frequency with wide busses and a high number of separate channels. However, this also requires data to be spread out over all channels to reach the full throughput. Previous research relied on manual HBM data partitioning schemes and handled each channel as an entirely independent entity. this paper in contrast also considers scalable hardware adaptions and approaches system design holistically. In this process we first analyze the problem with real world measurements on a Xilinx HBM FPGA. then we derive several architectural changes to improve throughput and ease accelerator design. Finally, a Roofline based model to more accurately estimate the expected performance in advance is presented. With these measures we were able to increase the throughput by up to 3.78x with random and 40.6x with certain strided access patterns compared to Xilinx' state-of-the-art switch fabric.

关键词： Field Programmable Gate Arrays (FPGA) High-Bandwidth Memory (HBM) Computational Modeling

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Leveraging PaRSEC Runtime Support to Tackle Challenging 3D Data-Sparse Matrix Problems 35

Leveraging PaRSEC Runtime Support to Tackle Challenging 3D D...

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35th ieee international parallel and distributed processing symposium (IPDPS)

作者： Cao, Qinglei Pei, Yu Akbudak, Kadir Bosilca, George Ltaief, Hatem Keyes, David Dongarra, Jack Univ Tennessee Innovat Comp Lab Knoxville TN 37996 USA King Abdullah Univ Sci & Technol Extreme Comp Res Ctr Div Comp Elect & Math Sci & Engn Thuwal Saudi Arabia ASELSAN Res Ctr Ankara Turkey Oak Ridge Natl Lab Oak Ridge TN USA Univ Manchester Manchester Lancs England

ISBN: (纸本)9781665440660

the task-based programming model associated with dynamic runtime systems has gained popularity for challenging problems because of workload imbalance, heterogeneous resources, or extreme concurrency. During the last decade, low-rank matrix approximations-where the main idea consists of exploiting data sparsity, typically by compressing off-diagonal tiles up to an application-specific accuracy threshold-have been adopted to address the curse of dimensionality at extreme scale. In this paper, we create a bridge between the runtime and the linear algebra by communicating knowledge of the data sparsity to the runtime. We design and implement this synergistic approach with high user productivity in mind, in the context of the PaRSEC runtime system and the HiCMA numerical library. this requires extending PaRSEC with new features to integrate rank information into the dataflow so that proper decisions can be made at runtime. We focus on the tile low-rank (TLR) Cholesky factorization for solving 3D data-sparse covariance matrix problems arising in environmental applications. In particular, we employ the 3D exponential model of the Match] matrix kernel, which exhibits challenging nonuniform high ranks in off-diagonal tiles. We first provide dynamic data structure management driven by a performance model to reduce extra floating-point operations. Next, we optimize the memory footprint of the application by relying on a dynamic memory allocator, and supported by a rank-aware data distribution to cope with the workload imbalance. Finally, we expose further parallelism using kernel recursive formulations to shorten the critical path. Our resulting high-performance implementation outperforms existing data-sparse TLR Cholesky factorization by up to 7-fold on a large-scale distributed-memory system, while minimizing the memory footprint up to a 44-fold factor. this multidisciplinary work highlights the need to empower runtime systems beyond their original duty of task scheduling fo

关键词： Low-rank matrix computations Task-based programming model Dynamic runtime system Asynchronous executions and load balancing High-performance computing User productivity Environmental applications

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