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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

共 2574 条记录，以下是231-240 订阅

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Using the Translation Lookaside Buffer to Map threads in parallel applications Based on Shared Memory

Using the Translation Lookaside Buffer to Map Threads in Par...

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Cruz, Eduardo H. M. Diener, Matthias Navaux, Philippe O. A. Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil

ISBN: (纸本)9780769546759

the communication latency between the cores in multiprocessor architectures differs depending on the memory hierarchy and the interconnections. With the increase of the number of cores per chip and the number of threads per core, this difference between the communication latencies is increasing. therefore, it is important to map the threads of parallel applications taking into account the communication between them. In parallel applications based on the shared memory paradigm, the communication is implicit and occurs through accesses to shared variables. For this reason, it is difficult to detect the communication pattern between the threads. Traditional approaches use simulation to monitor the memory accesses performed by the application, requiring modifications to the source code and drastically increasing the overhead. In this paper, we introduce a new light-weight mechanism to detect the communication pattern of threads using the Translation Lookaside Buffer (TLB). Our mechanism relies entirely on hardware features, which makes the thread mapping transparent to the programmer and allows it to be performed dynamically by the operating system. Moreover, no time consuming task, such as simulation, is required. We evaluated our mechanism with the NAS parallel Benchmarks (NPB) and achieved an accurate representation of the communication patterns. Using the detected communication patterns, we generated thread mappings using a heuristic method based on the Edmonds graph matching algorithm. Running the applications with these mappings resulted in performance improvements of up to 15.3%, reducing the number of cache misses by up to 31.1%.

关键词： thread mapping parallel applications Shared memory TLB Translation Lookaside Buffer Interconnections Cache Misses

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A Fast Repair Code Based on Regular Graphs for distributed Storage Systems

A Fast Repair Code Based on Regular Graphs for Distributed S...

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Wang, Yan Wang, Xin Fudan Univ Sch Comp Sci Shanghai Key Lab Intelligent Informat Proc Shanghai 200433 Peoples R China

ISBN: (纸本)9780769546766

distributed storage systems (DSS) play an important role in data storage applications, since they provide high reliability for huge data storage requirement. As node failures are frequent in a large distributed storage system, the performance of repairing node failure causes many researchers' interests. In this paper, we propose a distributed storage code to minimize the coding complexity during the repairing process, at a cost of inducing larger redundancy. Our code construction is based on regular graphs and exploits simple look-up repair. We analyze the performance of the proposed code, and compare them with existing distributed storage codes. Analytical results show that the proposed code outperforms the others in terms of low repair complexity and disk I/O overhead.

关键词： distributed storage systems Erasure codes Regenerating codes

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ECCount: Efficient and Consistent Counter for high-speed network devices 15

ECCount: Efficient and Consistent Counter for high-speed net...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Wang, Junchang He, Wen Zhou, Ningning Li, Tao Fu, Xiong Nanjing Univ Posts & Telecommun Sch Comp Sci Jiangsu Key Lab Big Data Secur & Intelligent Proc Nanjing 210023 Jiangsu Peoples R China

ISBN: (纸本)9781538637906

Nowadays, 10Gbps and higher speed network devices have become ubiquitous. these devices typically exploit multiple CPU cores to process packets to avoid overwhelming a single CPU core. the involving of multiple cores, however, brings tricky parallel programming issues. One of them is the miscount in statistical counter, which is the algorithm that has been widely used in high-speed network devices to track fundamental information such as the number of packets received and transmitted. As a result, modern high-speed network devices merely provides weak consistency guarantee on the counting results it returns;that is, the returned results may be inaccurate. this paper first analyses the miscount issue in modern high-speed network devices. then we present ECCount, a novel counting algorithm which (1) is competitive to the best known solutions in performance, and (2) provides strong consistency guarantee in counting results returned. Experiments show that it takes ECCount 10ns and 1,500ns to perform an update operation and a read operation, respectively. And the counting results returned are accurate.

关键词： lock-free counting algorithm strong consistency

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DAG Scheduling Considering parallel Execution for High-Load processing on Clustered Many-core Processors 26

DAG Scheduling Considering Parallel Execution for High-Load ...

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26th ieee/ACM international symposium on distributed Simulation and Real Time applications (DS-RT)

作者： Okamura, Ryo Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan

ISBN: (数字)9781665497992

ISBN: (纸本)9781665497992

In recent years, high computational power has been required for computer platforms to support complex systems such as self-driving systems. Clustered many-core processors and directed acyclic graphs (DAGs), which can represent dependencies and parallelism of task processing, have attracted much attention as solutions to this problem. Previous studies on scheduling DAGs on multi-core processors have attempted to reduce the makespan (i.e., time it takes for a task to complete) by increasing the number of processes that can be executed in parallel. However, in self-driving systems, such as those utilizing clustered many-core processors, it is impossible to sufficiently increase the utilization of processor cores due to high-load processing. In this paper, a scheduling method is proposed to improve the utilization of processor cores by parallel executing high-load processes in parallel across multiple cores. the proposed method can reduce the makespan of DAGs performing high-load processing on clustered many-core processors.

关键词： clustered many-core processors DAG work-conserving schedule list scheduling

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OLAP Aggregation Based on Dimension-oriented Storage

OLAP Aggregation Based on Dimension-oriented Storage

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Zhao Jing-hua Song Ai-mei Song Ai-bo Shandong Univ Sci & Technol Coll Informat Sci & Engn Qingdao Peoples R China Southeast Univ Sch Comp Sci & Engn Nanjing Peoples R China

ISBN: (纸本)9780769546766

OLAP (online analytical processing) applications are based on a variety of aggregate queries on large-scale data. As aggregation is always performed on columns, traditional row-oriented storage, in which all the columns of a data row are stored together, has seriously restricted its performance. this paper proposes a dimension-oriented storage model based on HBase, and a new parallel aggregation technique, which accomplishes aggregation operations with parallel MapReduce jobs. Finally, compared with Hive on standard TPC-H data set, our technique is demonstrated to improve performance of core aggregate operations significantly.

关键词： OLAP (online analytical processing) dimension-oriented storage aggregation MapReduce

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Controlling the Memory Subscription of distributed applications with a Task-Based Runtime System 30

Controlling the Memory Subscription of Distributed Applicati...

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30th ieee international parallel and distributed processing symposium (IPDPS)

作者： Sergent, Marc Goudin, David thibault, Samuel Aumage, Olivier Inria Bordeaux Talence France CEA CESTA Le Barp France Univ Bordeaux Talence France

ISBN: (纸本)9781509036820

the ever-increasing supercomputer architectural complexity emphasizes the need for high-level parallel programming paradigms. Among such paradigms, task-based programming manages to abstract away much of the architecture complexity while efficiently meeting the performance challenge, even at large scale. Dynamic run-time systems are typically used to execute task-based applications, to schedule computation resource usage and memory allocations. While computation scheduling has been well studied, the dynamic management of memory resource subscription inside such run-times has however been little explored. this paper studies the cooperation between a task-based distributed application code and a run-time system engine to control the memory subscription levels throughout the execution. We show that the task paradigm allows to control the memory footprint of the application by throttling the task submission flow rate, striking a compromise between the performance benefits of anticipative task submission and the resulting memory consumption. We illustrate the benefits of our contribution on a compressed dense linear algebra distributed application.

关键词： memory control task-based run-time systems compressed linear algebra distributed computing

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A Reconfigurable High Performance ASIP Engine for Image Signal processing

A Reconfigurable High Performance ASIP Engine for Image Sign...

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26th ieee international parallel and distributed processing symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Liao, Hsuanchun Asri, Mochamad Isshiki, Tsuyoshi Li, Dongju Kunieda, Hiroaki Tokyo Inst Technol Dept Commun & Integrated Syst Tokyo 152 Japan

ISBN: (纸本)9780769546766

Emerging digital television applications and the conventional MPSoC architectures encounter drastically increasing performance and flexibility requirement. To display high quality of images on the display devices, several image processing has to be performed. However, these algorithms are nonstandard and change case by case. It is difficult to achieve real time processing by using general purpose processor or DSP. In this paper, we present a reconfigurable Application Specific Instruction-set Processor (ASIP) which can perform several image processing algorithms by using the same datapath. It can complete several 1D filtering processing within 8 cycle/pixel;performing 16 times higher performance compare to conventional RISC processor. the performance of this ASIP can achieve the requirement of FullHD(1920x1080) application.

关键词： ASIP Image processing

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parallel Implementation of SHA256 on Multizone Heterogeneous Systems 21

Parallel Implementation of SHA256 on Multizone Heterogeneous...

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21st ieee international symposium on parallel and distributed processing with applications, 13th ieee international Conference on Big Data and Cloud Computing, 16th ieee international Conference on Social Computing and Networking and 13th international Conference on Sustainable Computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Luo, Yongtao Liu, Jie Xiao, Tiaojie Gong, Chunye National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory Laboratory of Digitizing Program for Frontier Equipment Changsha China National Supercomputer Center in Tianjin Tianjin China

ISBN: (纸本)9798350329223

SHA-256 plays an important role in widely used applications, such as data security, data integrity, digital signatures, and cryptocurrencies. However, most of the current optimized implementations of SHA-256 are based on CPUs or dedicated hardware, such as ASICs and FPGAs. Consequently, there is a need to explore whether new heterogeneous parallel framework can improve the computational performance of the hash function. To address this issue, we conducted a study on the MT-3000 platform, which is a special architecture processor for the next-generation exascale prototype supercomputer. We proposed MT-SHA256, a heterogeneous multistage parallel implementation for hashing multiple messages on the MT-3000. Combining the architectural features of this processor, we developed an effective solution that significantly improved the computational performance of SHA-256. As a result, MT-SHA256 achieved a maximum throughput of 1045.68 MB/s on a single acceleration core of MT-3000. this is 9.84x higher than the C code implementation on one CPU core of MT-3000. We also performed a scalability test and found that MT-SHA256 achieved a throughput of 98.04 GB/s on a computing node, and extended to 512 nodes (2048 acceleration clusters) on this system with good scalability. © 2023 ieee.

关键词： Hash functions

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Topology-aware VM Placement for Network Optimization in Cloud Data Centers 15

Topology-aware VM Placement for Network Optimization in Clou...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Lian, Zhen Li, Xin Qin, Xiaolin Nanjing Univ Aeronaut & Astronaut Coll Comp Sci & Technol Nanjing Jiangsu Peoples R China Collaborat Innovat Ctr Novel Software Technol & I Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781538637906

Cloud data centers are hosting more and more complicated applications or services. this makes the network bandwidth becoming essential and critical for the normal application conduction or service provision. Hence, it is necessary to consider the network issue appropriately when deploying virtual machines (VMs) to avoid the network bottleneck and to guarantee the quality of services. In this paper, we focus on the VM placement problem for minimizing the maximal link utilization to avoid network congestion. We formulate the VM placement problem by representing the user requests with resource topologies, and prove the problem to be NP-hard. We present a heuristic algorithm based on the graph theory, which takes the resource topologies into account. the basic idea is to divide the requested VMs into servers with low network communication cost by analyzing the resource topology. We conduct extensive simulations, and the results show that our algorithm has a significant performance improvement on reducing network occupation compared to the best-fit strategy and divide-and-conquer strategy.

关键词： Cloud data center graph theory network optimization subset-sum problem virtual machine placement

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An Efficient Hardware Prefetcher Exploiting the Prefetch Potential of Long-Stride Access Pattern on Virtual Address 15

An Efficient Hardware Prefetcher Exploiting the Prefetch Pot...

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15th ieee international symposium on parallel and distributed processing with applications (ISPA) / 16th ieee international Conference on Ubiquitous Computing and Communications (IUCC)

作者： Tian, Teng Wang, Tianqi Jin, Xi Univ Sci & Technol China Chinese Acad Sci Sch Phys Sci Key Lab Strongly Coupled Quantum Matter Phys Hefei Anhui Peoples R China

ISBN: (纸本)9781538637906

Large scale computing and applications with large data sets often cause high cache miss rate because of using array of structures or linked-list data structure. When traversing these data structures, the memory accesses may have constant long strides across pages on virtual address (VA), but mostly scatter over the physical address (PA). therefore, conventional stride prefetcher (SP) based on PA cannot prefetch data efficiently here. In this paper, we propose a hardware data prefetching design named Virtual Address-based Stride Prefetcher (VASP) to exploit the prefetch potential of long-stride access pattern on VA. VASP detects the access strides on VA including those cross pages, then it predicts a new VA and prefetches data after address translation. We implement VASP in the gem5 simulator and use SPEC CPU2006 integer benchmarks to evaluate its performance. Our simulation results show that, compared with SP, applying VASP to caches offers up to 43% performance improvement in the mcf benchmark, and improves the overall performance by 6%.

关键词： prefetcher virtual address performance

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