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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

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Sequence Alignment on Massively parallel Heterogeneous Systems

Sequence Alignment on Massively Parallel Heterogeneous Syste...

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ieee international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Aleksandr Drozd Naoya Maruyama Satoshi Matsuoka Graduate School of Information Science and Technology Tokyo Institute of Technology Meguro Tokyo Japan

ISBN: (纸本)9781467309745

Bioinformatics is a quickly emerging area of science with many important applications to human life. Sequence alignment in various forms is one of the main instruments used in bioinformatics. this work is motivated by the ever-increasing amount of sequence data that requires more and more computation power for its processing. this task calls for new GPU-based systems and their higher computational potential and energy efficiency as compared to CPUs. We address the problem of facilitating faster sequence alignment using modern multi-GPU clusters. Our initial step was to develop a fast and scalable GPU exact short sequence aligner. We used matching algorithm with small memory footprint based on Burrows-Wheeler transform. We developed a mathematical model of computation and communication costs to find optimal memory partitioning strategy for index and queries. Our solution achieves 10 times speedup over previous implementation based on suffix array on one GPU and scales to multiple GPUs. Our next step will be to adapt the suggested data structure and performance model for multi-node multi-GPU approximate sequence alignment. It is also planned to use exact matching to detect common regions in large sequences and use it as an intermediate step in full-scale genome comparison.

关键词： Indexes Graphics processing unit Bioinformatics Genomics Performance evaluation Arrays Complexity theory

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Object-distribution analysis for program decomposition and re-clustering

Object-distribution analysis for program decomposition and r...

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international symposium on parallel and distributed processing (IPDPS)

作者： R. Stahl F. Catthoor D. Verkest IMEC vzw Leuven Belgium

the next-generation of embedded systems confronts the designer with multi-processor systems both for performance and energy reasons. Exploiting task-level parallelism in combination with loop-level parallelism is becoming crucial. the challenge is to build compiler tools for the exploration of these types of parallelism. To achieve this goal, we have designed a transformation framework for analysis and extraction of the potential parallelism in sequential object-oriented programs. We present an inter-procedural, compositional, context and flow-sensitive algorithm for analysis of object distribution in sequential object-oriented programs. Our technique consists of three main phases: compositional inter-procedural object-distribution analysis, construction of minimal hierarchical object-distribution graph, and graph rendering using constrained force-directed layout. Integration of these algorithms allows us to reduce number of prospective program decompositions with respect to program flow and object-distribution properties. the visualisation environment further extends usability of our tools for employment of semi-automated as well as fully-automated heuristics with further constraints on definition of the final task boundaries. We demonstrate the usability of our approach on a number of realistic Java applications.

关键词： Algorithm design and analysis Embedded system Visualization Usability Java Energy efficiency Pipeline processing Performance analysis Employment Performance loss

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Improving the parallelism and concurrency in decoupled architectures

Improving the parallelism and concurrency in decoupled archi...

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international symposium on parallel and distributed processing (IPDPS)

作者： L. John R. Radhakrisnan Electrical and Computer Engineering University of Texas Austin Austin TX USA

Concurrency between access and execution has been exploited by queues in many decoupled access-execute architectures, but data dependent control dependencies often prohibit prefetching of data to queues. this paper investigates a technique to facilitate anticipatory loading to queues even in presence of data dependent control dependencies. the proposed method consists of fetching along one or both paths of a data dependent control dependency and inserting consume instructions in appropriate paths to consume the unnecessarily fetched data. the compiler hoists load instructions above control dependencies as in conventional load hoisting techniques. the technique is seen to be very effective in programs with data dependent if-then-else's. We also present an architecture with multiple access units, the mLSU architecture, which parallelizes the access process. Simulation experiments illustrate that multiple access units improve the performance if access processor instruction issue is a bottleneck.

关键词： Concurrent computing Computer architecture Processor scheduling Dynamic scheduling parallel processing Buffer storage Computer aided instruction Computer applications Pipelines Prefetching

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D1HT: a distributed one hop hash table 06

D1HT: a distributed one hop hash table

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international symposium on parallel and distributed processing (IPDPS)

作者： L.R. Monnerat C.L. Amorim Comput. & Syst. Eng. Fed. Univ. of Rio de Janeiro Brazil COPPE-Computer and Systems Engineering Federal University of Rio de Janeiro Brazil

ISBN: (纸本)9781424400546

distributed hash tables (DHTs) have been used in a variety of applications, but most DHTs so far have opted to solve lookups with multiple hops, which sacrifices performance in order to keep little routing information and minimize maintenance traffic. In this paper, we introduce D1HT, a novel single hop DHT that is able to maximize performance with reasonable maintenance traffic overhead even for huge and dynamic peer-to-peer (P2P) systems. We formally define the algorithm we propose to detect and notify any membership change in the system, prove its correctness and performance properties, and present a quarantine-like mechanism to reduce the overhead caused by volatile peers. Our analyses show that D1HT has reasonable maintenance bandwidth requirements even for very large systems, while presenting at least twice less bandwidth overhead than previous single hop DHT

关键词： Routing Bandwidth Peer to peer computing Telecommunication traffic Application software Delay distributed computing Systems engineering and theory Change detection algorithms Mechanical factors

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Using Multiple threads to Accelerate Single thread Performance

Using Multiple Threads to Accelerate Single Thread Performan...

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international symposium on parallel and distributed processing (IPDPS)

作者： Zehra Sura Kevin OBrien Jose Brunheroto IBM T.j. Watson Research Center Yorktown Heights New York USA

ISBN: (纸本)9781479938018

Computing systems are being designed with an increasing number of hardware cores. To effectively use these cores, applications need to maximize the amount of parallel processing and minimize the time spent in sequential execution. In this work, we aim to exploit fine-grained parallelism beyond the parallelism already encoded in an application. We define an execution model using a primary core and some number of secondary cores that collaborate to speed up the execution of sequential code regions. this execution model relies on cores that are physically close to each other and have fast communication paths between them. For this purpose, we introduce dedicated hardware queues for low-latency transfer of values between cores, and define special "enque" and "deque" instructions to use the queues. Further, we develop compiler analyses and transformations to automatically derive fine-grained parallel code from sequential code regions. We implemented this model for exploiting fine-grained parallelization in the IBM XL compiler framework and in a simulator for the Blue Gene/Q system. We also studied the Sequoia benchmarks to determine code sections where our techniques are applicable. We evaluated our work using these code sections, and observed an average speedup of 1.32 on 2 cores, and an average speedup of 2.05 on 4 cores. Since these code sections are otherwise sequentially executed, we conclude that our approach is useful for accelerating single thread performance.

关键词： parallel processing Hardware Instruction sets Partitioning algorithms Registers Acceleration Benchmark testing

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Integrated parallelization of Computations and Visualization for Large-scale applications

Integrated Parallelization of Computations and Visualization...

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ieee international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Preeti Malakar Vijay Natarajan Sathish S. Vadhiyar Department of Computer Science and Automation Indian Institute of Science Bangalore India Department of Computer Science and Automation Supercomputer Education and Research Centre Indian Institute of Science Bangalore India

ISBN: (纸本)9781467309745

Critical applications like cyclone tracking and earthquake modeling require simultaneous high-performance simulations and online visualization for timely analysis. Faster simulations and simultaneous visualization enable scientists provide real-time guidance to decision makers. In this work, we have developed an integrated user-driven and automated steering framework that simultaneously performs numerical simulations and efficient online remote visualization of critical weather applications in resource-constrained environments. It considers application dynamics like the criticality of the application and resource dynamics like the storage space, network bandwidth and available number of processors to adapt various application and resource parameters like simulation resolution, simulation rate and the frequency of visualization. We formulate the problem of finding an optimal set of simulation parameters as a linear programming problem. this leads to 30% higher simulation rate and 25-50% lesser storage consumption than a naive greedy approach. the framework also provides the user control over various application parameters like region of interest and simulation resolution. We have also devised an adaptive algorithm to reduce the lag between the simulation and visualization times. Using experiments with different network bandwidths, we find that our adaptive algorithm is able to reduce lag as well as visualize the most representative frames.

关键词： Adaptation models Data visualization Computational modeling Bandwidth Visualization Meteorology Data models

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An experiment with high performance components for grid applications

An experiment with high performance components for grid appl...

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international symposium on parallel and distributed processing (IPDPS)

作者： M. Coppola M. Pasquali L. Presti M. Vanneschi Istituto di Scienza e Tecnologie dell''Informazione-Consiglio Nazionale delle Ricerche Pisa Italy Dipartimento di Informatica Università di Pisa Pisa Italy

In this paper we describe an experiment in building grid-aware software components as basic blocks for high-performance, adaptive grid computations. Within the *** project we are working to the enhancement of the coordination language approach of the ASSIST parallel programming environment to support high-performance software components, that can react to the changes occurring on dynamic execution platforms. We are currently evaluating expressiveness and performance issues also by integrating ASSIST compilation tools with various component frameworks. In the paper we discuss results about a graphical application made up of four CCM components, each one produced by automatic encapsulation of a parallel program. We evaluate performance behaviour by comparing the composite application with the equivalent ASSIST one, on three different testbeds: homogeneous and heterogeneous clusters, and a small grid over a WAN. We also report first results about an application manager component that applies a simple adaptive policy, reacting to pipeline unbalance, to vary the amount of employed computational resources.

关键词： parallel programming Application software Dynamic programming Testing Software performance Grid computing Concurrent computing High performance computing Encapsulation Wide area networks

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A Visual Network Analysis Method for Large-Scale parallel I/O Systems

A Visual Network Analysis Method for Large-Scale Parallel I/...

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international symposium on parallel and distributed processing (IPDPS)

作者： Carmen Sigovan Chris Muelder Kwan-Liu Ma Jason Cope Kamil Iskra Robert Ross University of California Davis USA Mathematics and Computer Science Division Argonne National Laboratory USA

ISBN: (纸本)9781467360661

parallel applications rely on I/O to load data, store end results, and protect partial results from being lost to system failure. parallel I/O performance thus has a direct and significant impact on application performance. Because supercomputer I/O systems are large and complex, one cannot directly analyze their activity traces. While several visual or automated analysis tools for large-scale HPC log data exist, analysis research in the high-performance computing field is geared toward computation performance rather than I/O performance. Additionally, existing methods usually do not capture the network characteristics of HPC I/O systems. We present a visual analysis method for I/O trace data that takes into account the fact that HPC I/O systems can be represented as networks. We illustrate performance metrics in a way that facilitates the identification of abnormal behavior or performance problems. We demonstrate our approach on I/O traces collected from existing systems at different scales.

关键词： Data visualization Software Histograms Servers Measurement Instruments Visualization

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A heterogeneous hierarchical solution to cost-efficient high performance computing

A heterogeneous hierarchical solution to cost-efficient high...

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international symposium on parallel and distributed processing (IPDPS)

作者： Z.B. Miled J.A.B. Fortes Sch. of Electr. & Comput. Eng. Purdue Univ. West Lafayette IN USA School of Electrical and Computer Engineering Purdue University West Lafayette IN USA

Two facts that suggest the desirability of a hierarchical approach to cost-effective high-performance computing are empirically established in this paper. the first fact is the temporal locality of programs with respect to the degree of parallelism. Two temporal (instruction and data) locality principles are identified and empirically established for a set of programs. the impact of this behavior is discussed with respect to the proposed heterogeneous multilevel architecture. the second fact that supports the hierarchical architecture is the cost-efficiency advantage of heterogeneous over homogeneous multiprocessor systems. An initial performance analysis is presented which quantifies this fact for the proposed heterogeneous hierarchical organization. the proposed multilevel processor configuration uses fast and costly resources sparingly to reduce sequential and low parallelism bottlenecks. the resulting organization tries to balance cost, speed and parallelism granularity.

关键词： High performance computing parallel processing Concurrent computing Costs Bridges Multiprocessing systems Research and development Application software Computer applications Environmental economics

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SWAPP: A Framework for Performance Projections of HPC applications Using Benchmarks

SWAPP: A Framework for Performance Projections of HPC Applic...

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ieee international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Sameh Sharkawi Don DeSota Raj Panda Stephen Stevens Valerie Taylor Xingfu Wu Systems and Technology Group IBM Austin USA Department of Computer Science and Engineering Texas A and M University USA

ISBN: (纸本)9781467309745

Surrogate-based Workload Application Performance Projection (SWAPP) is a framework for performance projections of High Performance Computing (HPC) applications using benchmark data. Performance projections of HPC applications onto various hardware platforms are important for hardware vendors and HPC users. the projections aid hardware vendors in the design of future systems and help HPC users with system procurement. SWAPP assumes that one has access to a base system and only benchmark data for a target system, the target system is not available for running the HPC application. Projections are developed using the performance profiles of the benchmarks and application on the base system and the benchmark data for the target system. SWAPP projects the performances of compute and communication components separately then combine the two projections to get the full application projection. In this paper SWAPP was used to project the performance of three NAS Multi-Zone benchmarks onto three systems (an IBM POWER6 575 cluster and an IBM Intel West mere x5670 both using an Infiniband interconnect and an IBM Blue Gene/P with a 3D Torus and Collective Tree interconnects), the base system is an IBM POWER5+ 575 cluster. the projected performance of the three benchmarks was within 11.44% average error magnitude and standard deviation of 2.64% for the three systems.

关键词： Benchmark testing Measurement Hardware Computational modeling Radiation detectors Mathematical model Runtime

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