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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

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Identifying Opportunities for Byte-Addressable Non-Volatile Memory in Extreme-Scale Scientific applications

Identifying Opportunities for Byte-Addressable Non-Volatile ...

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international symposium on parallel and distributed processing (IPDPS)

作者： Dong Li Jeffrey S. Vetter Gabriel Marin Collin McCurdy Cristian Cira Zhuo Liu Weikuan Yu Oak Ridge National Laboratory USA Aubum University USA

ISBN: (纸本)9781467309752

Future exascale systems face extreme power challenges. To improve power efficiency of future HPC systems, non-volatile memory (NVRAM) technologies are being investigated as potential alternatives to existing memories technologies. NVRAMs use extremely low power when in standby mode, and have other performance and scaling benefits. Although previous work has explored the integration of NVRAM into various architecture and system levels, an open question remains: do specific memory workload characteristics of scientific applications map well onto NVRAMs' features when used in a hybrid NVRAM-DRAM memory system? Furthermore, are there common classes of data structures used by scientific applications that should be frequently placed into NVRAM?In this paper, we analyze several mission-critical scientific applications in order to answer these questions. Specifically, we develop a binary instrumentation tool to statistically report memory access patterns in stack, heap, and global data. We carry out hardware simulation to study the impact of NVRAM for both memory power and system performance. Our study identifies many opportunities for using NVRAM for scientific applications. In two of our applications, 31% and 27% of the memory working sets are suitable for NVRAM. Our simulations suggest at least 27% possible power savings and reveal that the performance of some applications is insensitive to relatively long NVRAM write-access latencies.

关键词： Nonvolatile memory Instruments Phase change random access memory Resource management Memory management Power demand

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accULL: An User-directed Approach to Heterogeneous Programming

accULL: An User-directed Approach to Heterogeneous Programmi...

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international symposium on parallel and distributed processing with applications, ISPA

作者： Ruym'n Reyes Iv'n López Juan J. Fumero Francisco de Sande Department de EIO y Computación Universidad de La Laguna La Laguna Spain

the world of HPC is undergoing rapid changes and computer architectures capable to achieve high performance have broadened. the irruption in the scene of computational accelerators, like GPUs, is increasing performance while maintaining low cost per GFLOP, thus expanding the popularity of HPC. However, it is still difficult to exploit the new complex processor hierarchies. To adapt the message passing model to program heterogeneous CPU+GPUs environments is not an easy task. Furthermore, message passing does not seem to be the best choice from the programmer point of view. Traditional shared memory approaches like OpenMP are interesting to ease the popularization of these platforms, but the fact is that GPU devices are connected to the CPU through a bus and have a separate memory space. We need to find a way to deal with this issue at programming language level, otherwise, developers will spend most of their time focusing on low-level code details instead of algorithmic enhancements. the recent advent of the OpenACC standard for heterogeneous computing represents an effort in the direction of leveraging the development effort. this initiative, combined with future releases of the OpenMP standard, will converge into a fully heterogeneous framework that will cope the programming requirements of future computer architectures. In this work we present preliminary results of accULL, a novel implementation of the OpenACC standard, based on a source-to-source compiler and a runtime library. To our knowledge, our approach is the first providing support for both OpenCL and CUDA platforms under this new standard.

关键词： Graphics processing unit Kernel Standards Programming Runtime Computer architecture

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RC-BLAST: towards a portable, cost-effective open source hardware implementation

RC-BLAST: towards a portable, cost-effective open source har...

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international symposium on parallel and distributed processing (IPDPS)

作者： K. Muriki K.D. Underwood R. Sass ECE Department Clemson University Clemson SC USA Sandia National Laboratories Albuquerque NM USA ITTC University of Kansas Lawrence KS USA

Basic Local Alignment Search Tool (BLAST) is a standard computer application that molecular biologists use to search for sequence similarity in genomic databases. this paper describes the implementation of an FPGA-based hardware implementation designed to accelerate the BLAST algorithm. FPGA-based custom computing machines, more widely known as reconfigurable computing, are supported by a number of vendors and the basic cost of FPGA hardware is dramatically decreasing. Hence, the main objective of this project is to explore the feasibility of using this new technology to realize a portable, open source FPGA-based accelerator for the BLAST algorithm. the present design is targeted to an AceIIcard and the design is based on the latest version of BLAST available from NCBI. Since the entire application does not fit in hardware, a profile study was conducted that identifies the computationally intensive part of BLAST. An FPGA hardware component has been designed and implemented for this critical segment. the portability and cost-effectiveness of the design are discussed.

关键词： Open source hardware Biology computing Field programmable gate arrays Computer applications Genomics Bioinformatics Databases Algorithm design and analysis Acceleration Costs

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HydEE: Failure Containment without Event Logging for Large Scale Send-Deterministic MPI applications

HydEE: Failure Containment without Event Logging for Large S...

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international symposium on parallel and distributed processing (IPDPS)

作者： Amina Guermouche thomas Ropars Marc Snir Franck Cappello INRIA-Saclay Île-de-France Orsay France École Polytechnique Fédérale de Lausanne Lausanne Switzerland University of Illinois Urbana-Champaign Urbana IL USA

ISBN: (纸本)9781467309752

High performance computing will probably reach exascale in this decade. At this scale, mean time between failures is expected to be a few hours. Existing fault tolerant protocols for message passing applications will not be efficient anymore since they either require a global restart after a failure (check pointing protocols) or result in huge memory occupation (message logging). Hybrid fault tolerant protocols overcome these limits by dividing applications processes into clusters and applying a different protocol within and between clusters. Combining coordinated check pointing inside the clusters and message logging for the inter-cluster messages allows confining the consequences of a failure to a single cluster, while logging only a subset of the messages. However, in existing hybrid protocols, event logging is required for all application messages to ensure a correct execution after a failure. this can significantly impair failure free performance. In this paper, we propose HydEE, a hybrid rollback-recovery protocol for send-deterministic message passing applications, that provides failure containment without logging any event, and only a subset of the application messages. We prove that HydEE can handle multiple concurrent failures by relying on the send-deterministic execution model. Experimental evaluations of our implementation of HydEE in the MPICH2 library show that it introduces almost no overhead on failure free execution.

关键词： Protocols Checkpointing Message passing Libraries Fault tolerance Fault tolerant systems

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Efficient all-to-all broadcast schemes in distributed-memory parallel computers

Efficient all-to-all broadcast schemes in distributed-memory...

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ieee international symposium on High Performance Computing Systems and applications (HPCS)

作者： E. Oh I.A. Kanj Department of Computer Science Texas A and M University College Station TX USA School of Computer Science Telecommunications and Information Systems De Paul University Chicago IL USA

distributed-memory parallel computers refer to parallel computers in which each processor has its own private memory. In such a system, processors communicate information by exchanging messages via the interconnection network rather than storing it in shared memory. One of the important communication methods in such systems is data broadcasting. All-to-all broadcasting is the process in which each processor sends its message to all other processors, and receives messages from all other processors in the system. Two complexity elements are usually considered when measuring the performance of a distributed-memory parallel model: time complexity and message complexity. In this paper we develop an efficient communication scheme to reduce both the communication time and the message complexity in the star network model under the half-duplex and full-duplex communication capability. the complexity measures of our scheme are compared against known bounds to verify the efficiency of the suggested scheme.

关键词： Broadcasting Concurrent computing distributed computing parallel processing Telecommunication computing Costs Computer science Microprocessors Hypercubes Information systems

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Using focused regression for accurate time-constrained scaling of scientific applications

Using focused regression for accurate time-constrained scali...

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international symposium on parallel and distributed processing (IPDPS)

作者： Brad Barnes Jeonifer Garren David K. Lowenthal Jaxk Reeves Bronis R. de Supinski Martin Schulz Barry Rountree Department of Computer Science University of Georgia USA Department of Statistics University of Georgia USA Department of Computer Science University of Arizona Tucson USA Lawrence Livemore National Laboratory USA

ISBN: (纸本)9781424464425

Many large-scale clusters now have hundreds of thousands of processors, and processor counts will be over one million within a few years. Computational scientists must scale their applications to exploit these new clusters. Time-constrained scaling, which is often used, tries to hold total execution time constant while increasing the problem size along with the processor count. However, complex interactions between parameters, the processor count, and execution time complicate determining the input parameters that achieve this goal. In this paper we develop a novel gray-box, focused regression-based approach that assists the computational scientist with maintaining constant run time on increasing processor counts. Combining application-level information from a small set of training runs, our approach allows prediction of the input parameters that result in similar per-processor execution time at larger scales. Our experimental validation across seven applications showed that median prediction errors are less than 13%.

关键词： Computer science Application software Data structures Statistics Laboratories Large-scale systems Concurrent computing Accuracy parallel processing Runtime

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Approaching a parallelized XML parser optimized for multi-coreprocessors

Approaching a parallelized XML parser optimized for multi-co...

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16th international symposium on High Performance distributed Computing 2007, HPDC'07 and Co-Located Workshops

作者： Head, Michael R. Govindaraju, Madhusudhan Grid Computing Research Laboratory Binghamton University P.O. Box 6000 Binghamton NY 13902-6000

ISBN: (纸本)159593717X

Very large scientific datasets are increasingly becoming available in XML formats. At the same time, multi-core processing is increasingly becoming available on desktop- and laptop-class computing machines. Unfortunately, most XML parsers are still using algorithms that are inherently serial, which show little improvement on newer computing hardware. the current XML implementation landscape does not adequately meet the performance requirements of large scale applications. thus far, applications using Web services (in the grid community, for example) have largely focused on XML protocol standardization and tool building efforts, and not on addressing the performance bottlenecks when dealing with large volumes of XML data. Generic parallel parsing has been studied in depth over the past thirty years. However, as yet, these results have not been applied to the problem of XML parsing. XML documents have some structural properties that make it more amenable to parallelized parsing than general context-free languages. As has been previously shown, XML parsers spend a large percentage of time tokenizing the input in aninherently serial process, typically running a deterministic finite automaton on the input. Our initial approach, described here, separates the process of parsing the XML from the process of reading the input. We take a well-known high performance parser, Piccolo, and apply two different strategies, Runahead and Piped, and examine the timing of the file read time and hence the overall time to parse large scientific XML files. Under the conditions tested here, performance decreases. Copyright 2007 ACM.

关键词： parallel programming

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Characterizing secure dynamic Web applications scalability

Characterizing secure dynamic Web applications scalability

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international symposium on parallel and distributed processing (IPDPS)

作者： J. Guitart V. Beltran D. Carrera J. Torres E. Ayguade European Center for Parallelism of Barcelona CEPBA Computer Architecture Department Technical University of Catalonia Barcelona Spain

Security in the access to Web contents and the interaction with Web sites is becoming one of the most important issues in Internet. Servers need to provide certain levels of security so that the user feels comfortable when running the applications that provide the services he/she requires. HTTP over SSL is the most used solution, providing mutual authentication between the two interacting parts. the SSL protocol does not introduce complexity in Web applications but increases the computational demand on the server, reducing its capacity to serve large number of clients and increasing the time to serve them. In order to compensate the degradation in the quality of service, the server needs to be upgraded with additional resources, mainly processors and memory. In this paper we analyze the scalability of servers that run secure dynamic Web applications. We analyze how the server behaves when it is stressed with different number of clients and how the quality of service is degraded. We perform a detailed analysis of the server behavior and analyze the impact of adding more processors to the system that runs the server. the analysis is done using a fine-grained analysis framework that considers all levels in the application server execution (i.e. application, server, JVM and OS kernel). the RUBiS auction site benchmark is used to stress a Tomcat application server running on a commodity 4-way multiprocessor Intel platform with Linux.

关键词： Scalability Web server Degradation Quality of service Performance analysis Internet Authentication Protocols Kernel Stress

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A Framework for Lattice QCD Calculations on GPUs

A Framework for Lattice QCD Calculations on GPUs

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international symposium on parallel and distributed processing (IPDPS)

作者： F.T. Winter M.A. Clark R.G. Edwards B. Joó Thomas Jefferson National Accelerator Facility Newport News VA USA NVIDIA Corporation Santa Clara CA USA

ISBN: (纸本)9781479938018

Computing platforms equipped with accelerators like GPUs have proven to provide great computational power. However, exploiting such platforms for existing scientific applications is not a trivial task. Current GPU programming frameworks such as CUDA C/C++ require low-level programming from the developer in order to achieve high performance code. As a result porting of applications to GPUs is typically limited to time-dominant algorithms and routines, leaving the remainder not accelerated which can open a serious Amdahl's law issue. the Lattice QCD application Chroma allows us to explore a different porting strategy. the layered structure of the software architecture logically separates the data-parallel from the application layer. the QCD Data-parallel software layer provides data types and expressions with stencil-like operations suitable for lattice field theory. Chroma implements algorithms in terms of this high-level interface. thus by porting the low-level layer one effectively ports the whole application layer in one swing. the QDP-JIT/PTX library, our reimplementation of the low-level layer, provides a framework for Lattice QCD calculations for the CUDA architecture. the complete software interface is supported and thus applications can be run unaltered on GPU-based parallel computers. this reimplementation was possible due to the availability of a JIT compiler which translates an assembly language (PTX) to GPU code. the existing expression templates enabled us to employ compile-time computations in order to build code generators and to automate the memory management for CUDA. Our implementation has allowed us to deploy the full Chroma gauge-generation program on large scale GPU-based machines such as Titan and Blue Waters and accelerate the calculation by more than an order of magnitude.

关键词： Graphics processing units Lattices Kernel Libraries Computer architecture Indexes Generators

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Extending OpenSHMEM for GPU Computing

Extending OpenSHMEM for GPU Computing

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international symposium on parallel and distributed processing (IPDPS)

作者： S. Potluri D. Bureddy H. Wang H. Subramoni D.K. Panda Department of Computer Science and Engineering Ohio State University USA

Graphics processing Units (GPUs) are becoming an integral part of modern supercomputer architectures due to their high compute density and performance per watt. In order to maximize utilization, it is imperative that applications running on these clusters have low synchronization and communication overheads. Partitioned Global Address Space (PGAS) models provide an attractive approach for developing parallel scientific applications. Such models simplify programming through the abstraction of a shared memory address space while their one-sided communication primitives allow for efficient implementation of applications with minimum synchronization. OpenSHMEM is a library-based programming model that is gaining popularity. However, the current OpenSHMEM standard does not support direct communication from GPU device buffers. It requires data to be copied to the host memory before OpenSHMEM calls can be made. Similarly, data has to moved to the GPU explicitly by remote processes. this severely limits the programmability and performance of GPU applications. In this paper we provide extensions to the OpenSHMEM model which allow communication calls to be made directly on the GPU memory. the proposed extensions are interoperable with the two most popular GPU programming frameworks: CUDA and OpenCL. We present designs for an efficient OpenSHMEM runtime which transparently provide high-performance communication between GPUs in different inter-node and intra-node configurations. To the best of our knowledge this is the first work that enables GPU-GPU communication using the OpenSHMEM model for both CUDA and OpenCL computing frameworks. the proposed extensions to OpenSHMEM, coupled with the high-performance runtime, improve the latency of GPU-GPU shmem getmem operation by 90%, 40% and 17%, for intra-IOH (I/O Hub), inter-IOH and inter-node configurations. It improves the performance of OpenSHMEM atomics by up to 55% and 52%, for intra-IOH and inter-node GPU configurations respect

关键词： Graphics processing units Runtime Context Computational modeling Electronics packaging Programming Kernel

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