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Performance and Practicability of Dynamic Adaptation for parallel Computing

Performance and Practicability of Dynamic Adaptation for Par...

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international symposium on High Performance distributed Computing

作者： J. Buisson F. Andre J.-L. Pazat IRISA/INSA de Rennes Rennes France Université de Rennes 1 Rennes France

Since the concept of grid computing has emerged; one of the major challenges consists in making applications able to benefit efficiently from the huge amount of resources with out burdening the developer. Observing that grid computing environments are dynamic, adaptability has been proposed as a way to tackle this problem. Adaptability is in deed the ability of applications to modify themselves according to their actual environment. It guarantees that they continuously behave in the best possible way despite environmental changes. In the context of grid computing, environmental changes concern mostly processor and network availability because of resource sharing between applications, administrative tasks and failures

关键词： parallel processing Grid computing Monitoring Adaptation model Availability Resource management Feedback Pipelines Decision making Engines

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distributed online anomaly detection in high-content screening

Distributed online anomaly detection in high-content screeni...

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ieee international symposium on Biomedical Imaging

作者： Adam Goode Rahul Sukthankar Lily Mummert Mei Chen Jeffrey Saltzman David Ross Stacey Szymanski Anil Tarachandani M. Satyanarayanan Carnegie Mellon University USA Intel Research Pittsburgh Merck and Company Inc.

this paper presents an automated, online approach to anomaly detection in high-content screening assays for pharmaceutical research. Online detection of anomalies is attractive because it offers the possibility of immediate corrective action, early termination, and redesign of assays that may require many hours or days to execute. the proposed approach employs assay-specific image processing within an assay-independent framework for distributed control, machine learning, and anomaly reporting. Specifically, we exploit coarse-grained parallelism to distribute image processing over several computing nodes while efficiently aggregating sufficient statistics across nodes. this architecture also allows us to easily handle geographically-distributed data sources. Our results from two applications, adipocyte quantitation and neurite growth estimation, confirm that this online approach to anomaly detection is feasible, efficient, and accurate.

关键词： Image processing Pharmaceuticals Termination of employment distributed control Machine learning parallel processing Concurrent computing distributed computing Statistical distributions Computer architecture

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Compiling C/C++ SIMD Extensions for Function and Loop Vectorizaion on Multicore-SIMD Processors

Compiling C/C++ SIMD Extensions for Function and Loop Vector...

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ieee international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Xinmin Tian Hideki Saito Milind Girkar Serguei V. Preis Sergey S. Kozhukhov Aleksei G. Cherkasov Clark Nelson Nikolay Panchenko Robert Geva Mobile Computing and Compilers Software and Service Group Intel Corporation Santa Clara CA USA Software and Service Group Mobile Computing and Compilers Intel Corporation Novosibirsk Russia

ISBN: (纸本)9781467309745

SIMD vectorization has received significant attention in the past decade as an important method to accelerate scientific applications, media and embedded applications on SIMD architectures such as Intel ® SSE, AVX, and IBM* AltiVec. However, most of the focus has been directed at loops, effectively executing their iterations on multiple SIMD lanes concurrently relying upon program hints and compiler analysis. this paper presents a set of new C/C++ high-level vector extensions for SIMD programming, and the Intel ® C++ product compiler that is extended to translate these vector extensions and produce optimized SIMD instruction sequences of vectorized functions and loops. For a function, our main idea is to vectorize the entire function for callers instead of just vectorizing loops (if any) inside the function. It poses the challenge of dealing with complicated control-flow in the function body, and matching caller and callee for SIMD vector calls while vectorizing caller functions (or loops) and callee functions. Our compilation methods for automatically compiling vector extensions are described. We present performance results of several non-trivial visual computing, computational, and simulation workloads, utilizing SIMD units through the vector extensions on Intel ® Multicore 128-bit SIMD processors, and we show that significant SIMD speedups (3.07x to 4.69x) are achieved over the serial execution.

关键词： Vectors Graphics processing unit Hardware Programming parallel processing Cloning

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RAPID: an end-system aware protocol for intelligent data transfer over lambda grids 06

RAPID: an end-system aware protocol for intelligent data tra...

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international symposium on parallel and distributed processing (IPDPS)

作者： A. Banerjee Wu-chun Feng B. Mukherjee D. Ghosal Department of Computer Science University of California슠Davis Davis CA USA Department of Computer Science Virginia Polytechnic Institute and State University Blacksburg VA USA Department of Computer Science University of California Davis Davis CA USA

ISBN: (纸本)9781424400546

Next-generation e-science applications will require the ability to transfer information at high data rates between distributed computing centers and data repositories. To support such applications, lambda grid networks have been built to provide large, on-demand bandwidth between end-points that are interconnected via optical circuit-switched lambdas. It is extremely important to develop an efficient transport protocol over such high-capacity, dedicated circuits. Because lambdas provide dedicated bandwidth between endpoints, they obviate the need for network congestion control. Consequently, past research has demonstrated that rate-based transport protocols, such as RBUDP, are more effective than TCP in transferring data over lambdas. However, while lambdas eliminate congestion in the network, they ultimately push the congestion to the endpoints - congestion that current rate-based transport protocols are ill-suited to handle. In this paper we introduce a "rate-adaptive protocol for intelligent delivery (RAPID)" of data that is lightweight and end-system performance-aware, so as to maximize end-to-end throughput while minimizing packet loss. Based on self monitoring of the dynamic task-priority at the receiving end-system, our protocol enables the receiver to proactively deliver feedback to the sender, so that the sender may adapt its sending rate to avoid congestion at the receiving end-system. this avoids large bursts of packet losses typically observed in current rate-based transport protocols. Over a 10-Gigabit link emulation of an optical circuit, RAPID reduces file-transfer time, and hence improves end-to-end throughput by as much as 25%

关键词： Transport protocols Optical feedback Optical receivers Bandwidth throughput distributed computing Integrated circuit interconnections Optical interconnections Optical fiber networks Ultraviolet sources

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DC-SIMD : Dynamic communication for SIMD processors

DC-SIMD : Dynamic communication for SIMD processors

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international symposium on parallel and distributed processing (IPDPS)

作者： Raymond Frijns Hamed Fatemi Bart Mesman Henk Corporaal Eindhovan University of Technology Eindhoven Noord-Brabant Netherlands

SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the huge amount of data-level parallelism in pixel-type operations, operating at a relatively low energy consumption rate. However, current SIMD architectures lack support for dynamic communication between processing elements, which is needed to efficiently map a set of non-linear algorithms. An architecture for dynamic communication support has been proposed, but this architecture needs large amounts of buffering to function properly. In this paper, three architectures supporting dynamic communication without the need of large amounts of buffering are presented, requiring 98% less buffer space. Cycle-true communication architecture simulators have been developed to accurately predict the performance of the different architectures. Simulations with several test algorithms have shown a performance improvement of up to 5x compared to a locally connected SIMD-processor. Also, detailed area models have been developed, estimating the three proposed architectures to have an area overhead of 30-70% compared to a locally connected SIMD architecture (like the IMAP). When memory is taken into account as well, the overhead is estimated to be 13-28%.

关键词： Computer architecture Process control Image processing Smart cameras parallel processing Pixel Costs Registers Energy consumption Predictive models

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Compiler assisted dynamic management of registers for network processors 06

Compiler assisted dynamic management of registers for networ...

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international symposium on parallel and distributed processing (IPDPS)

作者： R. Collins F. Alegre Xiaotong Zhuang S. Pande College of Computing Georgia Institute of Technology Atlanta GA USA

ISBN: (纸本)9781424400546

Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. threads switch context upon encountering long latency memory accesses and this way the parallelism and memory access can be overlapped. Context switches in the typical network processor architectures such as the IXP are designed to be very fast. However, the low overhead is partly achieved by leaving register management to programs, with minimal support from the hardware. the complexity of the multi-engine, multi-threaded environment makes manual register management a daunting task, which is better left to a compiler. However, a purely static analysis is unable to achieve full utilization of the register file due to conservative estimates of liveness. A register that is live across a context switch point must be considered live for the duration of all other threads, and so it must be assumed to be unavailable to other threads. In addition, aliasing further reduces the effectiveness of static analysis. the net effect is a large number of idle cycles that are still present after static optimization. We propose a dynamic solution that requires minimal software and hardware support. On the software side, we take a pre-allocated binary file and annotate the potential context switch instructions with information about the dead registers. On the hardware side, we try to rename the transfer registers and addresses to dead general purpose registers and update the usage of registers. We then replace the long-latency memory instructions with fast move instructions in the architecture using the dynamic context. the results show up to 51% reduction in idle cycles and up to H% increase in the throughput for hand coded applications on Intel IXP 1200 network processor

关键词： Dynamic compiler Registers Yarn Switches Hardware parallel processing Delay Programming profession Program processors Computer network management

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Automatic Offloading C++ Expression Templates to CUDA Enabled GPUs

Automatic Offloading C++ Expression Templates to CUDA Enable...

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ieee international symposium on parallel and distributed processing Workshops and Phd Forum (IPDPSW)

作者： Jie Chen Balint Joo William Watson III Robert Edwards Jefferson Laboratory The Scientific Computing Group Newport News VA USA Jefferson Laboratory The Theory Center Newport News VA USA

ISBN: (纸本)9781467309745

In the last few years, many scientific applications have been developed for powerful graphics processing units (GPUs) and have achieved remarkable speedups. this success can be partially attributed to high performance host callable GPU library routines that are offloaded to GPUs at runtime. these library routines are based on C/C++-like programming toolkits such as CUDA from NVIDIA and have the same calling signatures as their CPU counterparts. Recently, with the sufficient support of C++ templates from CUDA, the emergence of template libraries have enabled further advancement in code reusability and rapid software development for GPUs. However, Expression Templates (ET), which have been very popular for implementing data parallel scientific software for host CPUs because of their intuitive and mathematics-like syntax, have been underutilized by GPU development libraries. the lack of ET usage is caused by the difficulty of offloading expression templates from hosts to GPUs due to the inability to pass instantiated expressions to GPU kernels as well as the absence of the exact form of the expressions for the templates at the time of coding. this paper presents a general approach that enables automatic offloading of C++ expression templates to CUDA enabled GPUs by using the C++ metaprogramming technique and Just-In-Time (JIT) compilation methodology to generate and compile CUDA kernels for corresponding expression templates followed by executing the kernels with appropriate arguments. this approach allows developers to port applications to run on GPUs with virtually no code modifications. More specifically, this paper uses a large ET based data parallel physics library called QDP++ as an example to illustrate many aspects of the approach to offload expression templates automatically and to demonstrate very good speedups for typical QDP++ applications running on GPUs against running on CPUs using this method of offloading. In addition, this approach of automatic offloa

关键词： Graphics processing unit Arrays Kernel Libraries Vectors Lattices Runtime

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Beam-tracing domain decomposition method for urban acoustic pollution

Beam-tracing domain decomposition method for urban acoustic ...

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13th international symposium on distributed Computing and applications to Business,Engineering & Science（DCABES 2014）

作者： Guillaume Gbikpi-Benissan Frdric Magoulès Ecole Centrale Paris

this paper covers the fast solution of large acoustic problems on low-resources parallel platforms. A domain decomposition method is coupled with a dynamic load balancing scheme to efficiently accelerate a geometrical acoustic method. the geometrical method studied implements a beam-tracing method where intersections are handled as in a ray-tracing method. Beyond the distribution of the global processing upon multiple sub-domains, a second parallelization level is operated by means of multi-threading and shared memory *** experiments show that this method allows to handle large scale open domains for parallel computing purposes on few machines. Urban acoustic pollution arrising from car traffic was simulated on a large model of the Shinjuku district of Tokyo, Japan. the good speed-up results illustrate the performance of this new domain decomposition method.

关键词： Domain decomposition methods parallel and distributed computing Acoustics Ray-tracing methods Beam-tracing methods

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An intelligent system architecture for urban traffic control applications

An intelligent system architecture for urban traffic control...

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international symposium on parallel and distributed processing (IPDPS)

作者： M.I. Patel N. Ranganathan Department of Computer Science and Engineering University of South Florida Tampa FL USA

this paper describes an intelligent system architecture for urban traffic control which integrates a neural network and an expert system on silicon. the intelligent decision making system consists of a backpropagation based neural network for adaptive learning and a rule-based fuzzy expert system for decision making. Both the neural network and the expert system are implemented as linear systolic arrays. thus, the entire system can be realized in VLSI with a few basic cells. the architecture exploits the principles of pipelining and parallelism to the maximum possible extent in order to achieve high speed and throughput. the effectiveness of the proposed system is illustrated by mapping two application problems: (i) adaptive traffic light control and (ii) congestion detection and avoidance in urban traffic control. the proposed hardware can yield a real-time decision every 5 ns based on a 200 MHz clock.

关键词： Intelligent systems Traffic control Neural networks Intelligent networks Expert systems Decision making Silicon Backpropagation Adaptive systems Hybrid intelligent systems

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Extracting speedup from C-code with poor instruction-level parallelism

Extracting speedup from C-code with poor instruction-level p...

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international symposium on parallel and distributed processing (IPDPS)

作者： D. Kusic R. Hoare A.K. Jones J. Fazekas J. Foster Electrical and Computer Engineering University of Pittsburgh Pittsburgh PA USA

Scientific computing and multimedia applications frequently call loop-intensive functions that dominate execution time. Applying homogeneous, parallel processors (e.g. single-instruction, multiple-data (SIMD) and very-long instruction word (VLIW)) is a common approach to minimizing execution time. However, many benchmark applications offer disappointing degrees of instruction-level parallelism (ILP) that cause these architectures to fall short of expected performance gains. this paper presents findings on execution time speedup achieved by heterogeneous massively parallel processors - standard reduced instruction-set computing (RISC) CPUs tightly coupled with arrays of super-complex instruction-set computing (SuperCISC) datapaths on the same chip. SuperCISC datapaths are created by mapping frequently-called functions into reconfigurable hardware. Encouraging performance results from the RISC/SuperCISC architecture point to the efficiency of reconfigurable devices to support large numbers of parallel computational accelerators. Calls to SuperCISC functions can greatly expedite execution time when applied to CPUs that support extensible instruction sets. In this paper we show how SuperCISC functions can accelerate an application up to 25x over a 4-way VLIW. SuperCISC functions show superlinear speedup, a performance gain significantly greater than the software's ILP. SuperCISC functions also benefit from cycle compression, or a reduction of the idle cycle time for an operation to execute within a traditional CPU. Implementing software controls, or if-then-else statements, as hardware multiplexers within a SuperCISC function further advances performance.

关键词： Concurrent computing parallel processing VLIW Computer architecture Performance gain Computer aided instruction Reduced instruction set computing Hardware Software performance Scientific computing

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