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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

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Software-directed disk power management for scientific applications

Software-directed disk power management for scientific appli...

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international symposium on parallel and distributed processing (IPDPS)

作者： S.W. Son M. Kandemir A. Choudhary CSE Department Pennsylvania State University University Park PA USA ECE Department Northwestern University Evanston IL USA

Disk power consumption is becoming an increasingly important issue in high-end servers that execute large-scale data-intensive applications. In particular, array-based scientific codes can spend a significant portion of their power budget on the disk subsystem. Observing this, the prior research proposed several strategies, such as spinning down to low-power modes or adjusting the speed of the disk in lower RPM, to reduce power consumption on the disk subsystem. A common characteristic of most of these techniques is that they are reactive, in the sense that they make their decisions based on the disk access patterns observed during execution. While such techniques are certainly useful and the published studies reveal that they can be very effective in some cases, one can conceivably achieve better results by adopting a proactive scheme. Focusing on array-intensive scientific applications, this paper makes two important contributions. First, it presents a compiler-driven proactive approach to disk power management. In this approach, the compiler analyzes the application code and extracts the disk access pattern. It then uses this information to insert explicit disk power management calls in the appropriate places in the code. It also pre-activates a disk (placed into the low-power mode) before it is actually needed to eliminate the potential performance impact of disk power management. the second contribution of this paper is a code transformation approach that can be used to increase the savings coming from a disk power management scheme (whether reactive or proactive). Our experimental results with several scientific application codes show that both the proactive disk power management approach and the disk layout aware code transformations are beneficial from both power consumption and execution time perspectives.

关键词： Energy management Application software Energy consumption Power system management Pattern analysis Data mining Large-scale systems Cooling Voltage Operating systems

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Unlocking Personalized Healthcare on Modern CPUs/GPUs: three-way Gene Interaction Study

Unlocking Personalized Healthcare on Modern CPUs/GPUs: Three...

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international symposium on parallel and distributed processing (IPDPS)

作者： Diogo Marques Rafael Campos Sergio Santander-Jimé nez Zakhar Matveev Leonel Sousa Aleksandar Ilic INESC-ID Instituto Superior T&#x00E9 cnico Universidade de Lisboa Portugal Polytechnic School University of Extremadura Spain Intel Corporation Russia

Developments in Genome-Wide Association Studies have led to the increasing notion that future healthcare techniques will be personalized to the patient, by relying on genetic tests to determine the risk of developing a disease. To this end, the detection of gene interactions that cause complex diseases constitutes an important application. Similarly to many applications in this field, extensive data sets containing genetic information for a series of patients are used (such as Single-Nucleotide Polymorphisms), leading to high computational complexity and memory utilization, thus constituting a major challenge when targeting high-performance execution in modern computing systems. To close this gap, this work proposes several novel approaches for the detection of three-way gene interactions in modern CPUs and GPUs, making use of different optimizations to fully exploit the target architectures. Crucial insights from the Cache-Aware Roofline Model are used to ensure the suitability of the applications to the computing devices. An extensive study of the architectural features of 13 CPU and GPU devices from all main vendors is also presented, allowing to understand the features relevant to obtain high-performance in this bioinformatics domain. To the best of our knowledge, this study is the first to perform such evaluation for epistasis detection. the proposed approaches are able to surpass the performance of state-of-the-art works in the tested platforms, achieving an average speedup of 3.9× (7.3× on CPUs and 2.8× on GPUs) and maximum speedup of 10.6× on Intel UHD P630 GPU.

关键词： Performance evaluation distributed processing Computational modeling Graphics processing units Genomics Medical services Computer architecture

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Improving parallel IO Performance of Cell-based AMR Cosmology applications

Improving Parallel IO Performance of Cell-based AMR Cosmolog...

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international symposium on parallel and distributed processing (IPDPS)

作者： Yongen Yu Douglas H. Rudd Zhiling Lan Nickolay Y. Gnedin Andrey Kravtsov Jingjin Wu Department of Computer Science Illinois Institute of Technology Chicago IL USA Yale Center for Astronomy and Astrophysics Yale University New Heaven CT USA Theoretical Astrophysics Group Fenni National Accelerator Laboratory Batavia IL USA Department of Astronomy and Astrophysics University of Chicago Chicago IL USA

ISBN: (纸本)9781467309752

To effectively model various regions with different resolutions, adaptive mesh refinement (AMR) is commonly used in cosmology simulations. there are two well-known numerical approaches towards the implementation of AMR based cosmology simulations: block-based AMR and cell-based AMR. While many studies have been conducted to improve performance and scalability of block-structured AMR applications, little work has been done for cell-based simulations. In this study, we present a parallel IO design for cell-based AMR cosmology applications, in particular, the ART(Adaptive Refinement Tree) code. First, we design a new data format that incorporates a space filling curve to map between spatial and on-disk locations. this indexing not only enables concurrent IO accesses from multiple application processes, but also allows users to extract local regions without significant additional memory, CPU or disk space overheads. Second, we develop a flexible N-M mapping mechanism to harvest the benefits of N-N and N-1 mappings where N is number of application processes and M is a user-tunable parameter for number of files. It not only overcomes the limited bandwidth issue of an N-1 mapping by allowing the creation of multiple files, but also enables users to efficiently restart the application at a variety of computing scales. third, we develop a user-level library to transparently and automatically aggregate small IO accesses per process to accelerate IO performance. We evaluate this new parallel IO design by means of real cosmology simulations on production HPC system at TACC. Our preliminary results indicate that it can not only provide the functionality required by scientists (e.g., effective extraction of local regions and flexible process-to file mapping), but also significantly improve IO performance.

关键词： Indexes Computational modeling Adaptation models Subspace constraints Layout Numerical models Data models

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Iterative Krylov Methods for Acoustic Problems on Graphics processing Unit

Iterative Krylov Methods for Acoustic Problems on Graphics P...

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13th international symposium on distributed Computing and applications to Business,Engineering & Science（DCABES 2014）

作者： Abal-Kassim Cheik Ahamed Frdric Magoulès CUDA Research Center &Applied Mathematics and Systems Laboratory Ecole Centrale Paris

this paper deals with linear algebra operations on Graphics processing Unit(GPU) with complex number arithmetic using double precision. An analysis of their uses within iterative Krylov methods is presented to solve acoustic *** experiments performed on a set of acoustic matrices arising from the modelisation of acoustic phenomena inside a car compartment are collected, and outline the performance,robustness and effectiveness of our algorithms, with a speed-up up to 28 x for dot product, 9.8x for sparse matrix-vector product and solvers.

关键词： Linear algebra Iterative Krylov methods CSR matrix GPU CUDA Acoustic Helmholtz equation parallel computing

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Exploiting Geometric Partitioning in Task Mapping for parallel Computers

Exploiting Geometric Partitioning in Task Mapping for Parall...

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international symposium on parallel and distributed processing (IPDPS)

作者： Mehmet Deveci Sivasankaran Rajamanickam Vitus J. Leung Kevin Pedretti Stephen L. Olivier David P. Bunde Umit V. Çatalyürek Karen Devine Ohio State University Columbus OH US Sandia National Laboratories Albuquerque NM US Sandia National Laboratories Albuquerque New Mexico Knox College Galesburg IL The Ohio State University Columbus Ohio

We present a new method for mapping applications' MPI tasks to cores of a parallel computer such that communication and execution time are reduced. We consider the case of sparse node allocation within a parallel machine, where the nodes assigned to a job are not necessarily located within a contiguous block nor within close proximity to each other in the network. the goal is to assign tasks to cores so that interdependent tasks are performed by "nearby" cores, thus lowering the distance messages must travel, the amount of congestion in the network, and the overall cost of communication. Our new method applies a geometric partitioning algorithm to both the tasks and the processors, and assigns task parts to the corresponding processor parts. We show that, for the structured finite difference mini-app Mini Ghost, our mapping method reduced execution time 34% on average on 65,536 cores of a Cray XE6. In a molecular dynamics mini-app, Mini MD, our mapping method reduced communication time by 26% on average on 6144 cores. We also compare our mapping with graph-based mappings from the LibTopoMap library and show that our mappings reduced the communication time on average by 15% in MiniGhost and 10% in MiniMD.

关键词： Partitioning algorithms Program processors Resource management Measurement Libraries Network topology three-dimensional displays

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Efficient algorithms for block-cyclic redistribution of arrays

Efficient algorithms for block-cyclic redistribution of arra...

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international symposium on parallel and distributed processing (IPDPS)

作者： Young Won Lim P.B. Bhat V.K. Prasanna Department of EE-Systems University of Southern California Los Angeles CA USA

We present new algorithmic techniques for a classical research problem, runtime redistribution of an array from one block-cyclic layout to another. Our methodology for reducing communication overheads is based on a generalized circulant matrix formalism. Using this formalism, we derive direct, indirect, and hybrid communication schedules for the cyclic redistribution problem when the block size changes by an integer factor K. We have also developed formulae to estimate the timing performance of each of these schedules for a given parallel machine and redistribution problem. In our indirect communication schedule, blocks are moved from a source processor to a destination processor through intermediate "relay" processors. this reduces the number of communication steps by an order of magnitude, in comparison with previous approaches. this algorithm performs cyclic(x) to cyclic(Kx) redistribution on P processors in [log/sub 2/K]+2 steps. Implementations of these algorithms on the Cray T3D and on the IBM SP-2 show superior performance over previous approaches. Since our algorithms are developed using MPI, they can be easily ported to different application environments. Our techniques can be used in the design of scalable redistribution libraries, in efficient implementations of the REDISTRIBUTE directive of HPF and in developing parallel algorithms for various HPC applications.

关键词： Signal processing algorithms Processor scheduling parallel machines Algorithm design and analysis Libraries parallel algorithms High performance computing Program processors Programming profession Search problems

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Scalar Waving: Improving the Efficiency of SIMD Execution on GPUs

Scalar Waving: Improving the Efficiency of SIMD Execution on...

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international symposium on parallel and distributed processing (IPDPS)

作者： Ayse Yilmazer Zhongliang Chen David Kaeli Electrical and Computer Engineering Department Northeastern University Boston USA

GPUs take advantage of uniformity in program control flow and utilize SIMD execution to obtain execution efficiency. In SIMD execution, threads are batched into SIMD groups to share a common program counter and execute identical instructions on SIMD pipelines. Previous research has shown that there is a significant number of scalar instructions - instructions where different threads in a SIMD group execute using the same input operands and generate the exact same output - present in a range of applications. GPUs eliminate redundant fetches and decodes by utilizing a shared common pipeline front-end. However, most GPUs do not handle scalar instruction efficiently, allowing these instructions to be redundantly executed by the threads in a SIMD group. In this paper, we propose to use scalar execution to eliminate redundant execution of scalar instructions. We introduce scalar waving as a mechanism to batch scalar operations possessing the same PC and execute them as a group on SIMD lanes for efficiency. We also propose simultaneous execution of dynamically-formed scalar waves with SIMD groups to overcome the under-utilization of SIMD lanes when encountering divergence. We evaluate our work using 22 different GPU benchmarks taken from 4 different benchmark suites. We evaluate a range of configurations using timing simulation. Our results show that scalar waving can obtain up to a 25% improvement in performance on average. Our experiments also provide insight into the amount of performance gain that we can expect with scalar waving as a function of the scalar content, occupancy, and memory characteristics of the target application.

关键词： Registers Pipelines Instruction sets Graphics processing units Benchmark testing Computer architecture

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Power and Performance Characterization and Modeling of GPU-Accelerated Systems

Power and Performance Characterization and Modeling of GPU-A...

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international symposium on parallel and distributed processing (IPDPS)

作者： Yuki Abe Hiroshi Sasaki Shinpei Kato Koji Inoue Masato Edahiro Martin Peres Kyushu University Fukuoka Japan Nagoya University Nagoya Japan Laboratoire Bordelais de Recherche en Informatique Bordeaux France

Graphics processing units (GPUs) provide an order-of-magnitude improvement on peak performance and performance-per-watt as compared to traditional multicore CPUs. However, GPU-accelerated systems currently lack a generalized method of power and performance prediction, which prevents system designers from an ultimate goal of dynamic power and performance optimization. this is due to the fact that their power and performance characteristics are not well captured across architectures, and as a result, existing power and performance modeling approaches are only available for a limited range of particular GPUs. In this paper, we present power and performance characterization and modeling of GPU-accelerated systems across multiple generations of architectures. Characterization and modeling both play a vital role in optimization and prediction of GPU-accelerated systems. We quantify the impact of voltage and frequency scaling on each architecture with a particularly intriguing result that a cutting-edge Kepler-based GPU achieves energy saving of 75% by lowering GPU clocks in the best scenario, while Fermi- and Tesla-based GPUs achieve no greater than 40% and 13%, respectively. Considering these characteristics, we provide statistical power and performance modeling of GPU-accelerated systems simplified enough to be applicable for multiple generations of architectures. One of our findings is that even simplified statistical models are able to predict power and performance of cutting-edge GPUs within errors of 20% to 30% for any set of voltage and frequency pair.

关键词： Graphics processing units Benchmark testing Predictive models Educational institutions Optimization Multicore processing

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R256: A Research parallel Processor For Scientific Computation

R256: A Research Parallel Processor For Scientific Computati...

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Annual international symposium on Computer Architecture, ISCA

作者： T. Fukazawa T. Kimura M. Tomizawa K. Takeda Y. Itoh NTT LSI Laboratories Atsugi Japan NTT Electronics Technology Company Atsugi Japan

A scientific parallel processor called the R256 has been developed. the R256 is composed of 16X16 processing el- ements, and has the outstanding features of a " distributed parallel network " as well as on ieee 80-bit extended floating point computation ability. the computation accuracy, required by an exhaustive number of iterations in scientific computations, is resolved by the dedicated 80-bit VLSI processor, which was developed here for the R256. the innovative distributed parallel network was designed so as effectively resolve heavy communication problems, which are found in applications based on the Monte Carlo sim ulation technique. the R256 network was very economical at a hardware cost of /spl radic/N-folds (16 folds in this case) to that of an ideal full-crossbar switch, at the same time keeping the rates comparable to that of an ideal switch. the R256 demonstrates high performance of 2-GB/s data transfer rates and 500-MFLOPS computation rates on a semiconductor device simulation application.

关键词： Concurrent computing Computational modeling Switches Computer networks distributed computing Semiconductor devices Permission Very large scale integration parallel processing Computer architecture

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Scheduling from the perspective of the application 96

Scheduling from the perspective of the application

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international symposium on High Performance distributed Computing

作者： F. Berman R. Wolski Department of Computer Science and Engineering University of California San Diego La Jolla CA USA University of California San Diego La Jolla CA US Dept. of Comput. Sci. & Eng. California Univ. San Diego La Jolla CA USA

ISBN: (纸本)9780818675829

Metacomputing is the aggregation of distributed and high-performance resources on coordinated networks. With careful scheduling, resource-intensive applications can be implemented efficiently on metacomputing systems at the sizes of interest to developers and users. In this paper, we focus on the problem of scheduling applications on metacomputing systems. We introduce the concept of application-centric scheduling in which everything about the system is evaluated in terms of its impact on the application. Application-centric scheduling is used by virtually all metacomputer programmers to achieve performance on metacomputing systems. We describe two successful metacomputing applications to illustrate this approach, and describe AppLeS (Application-Level Scheduling) agents which generalize the application-centric scheduling approach. Finally, we show preliminary results which compare AppLeS-derived schedules with conventional strip and blocked schedules for a 2D Jacobi code.

关键词： Metacomputing Processor scheduling Concurrent computing Application software parallel processing High performance computing Strips Jacobian matrices Computer networks Contracts

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