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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

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Fast deterministic sorting on large parallel machines

Fast deterministic sorting on large parallel machines

引用

international symposium on parallel and distributed processing (IPDPS)

作者： T. Dachraoui L. Narayanan Department of Computer Science Concordia University Montreal QUE Canada

Many sorting algorithms that perform well on uniformly distributed data suffer significant performance degradation on non-random data. Unfortunately many real-world applications require sorting on data that is not uniformly distributed. In this paper we consider distributions of varying entropies. We describe A-Ranksort, a new sorting algorithm for parallel machines, whose behavior on input distributions of different entropies is relatively stable. Our algorithm is based on a deterministic strategy to find approximate ranks for all keys. We implemented A-Ranksort, B-Flashsort, Radixsort, and Bitonic sort on a 2048 processor Maspar MP-1. Our experiments show that A-Ranksort out-performs all the other algorithms on a variety of input distributions, when the output is required to be balanced. We are also able to provide bounds on the average-case and worst-case complexities of our algorithm, in terms of the costs of some chosen primitive operations. the predicted performance is very close to the empirical results, thus justifying our model.

关键词： Sorting parallel machines Algorithm design and analysis Computer science Application software Entropy Costs Predictive models Concurrent computing Topology

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Improving the parallelism and concurrency in decoupled architectures

Improving the parallelism and concurrency in decoupled archi...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： L. John R. Radhakrisnan Electrical and Computer Engineering University of Texas Austin Austin TX USA

Concurrency between access and execution has been exploited by queues in many decoupled access-execute architectures, but data dependent control dependencies often prohibit prefetching of data to queues. this paper investigates a technique to facilitate anticipatory loading to queues even in presence of data dependent control dependencies. the proposed method consists of fetching along one or both paths of a data dependent control dependency and inserting consume instructions in appropriate paths to consume the unnecessarily fetched data. the compiler hoists load instructions above control dependencies as in conventional load hoisting techniques. the technique is seen to be very effective in programs with data dependent if-then-else's. We also present an architecture with multiple access units, the mLSU architecture, which parallelizes the access process. Simulation experiments illustrate that multiple access units improve the performance if access processor instruction issue is a bottleneck.

关键词： Concurrent computing Computer architecture Processor scheduling Dynamic scheduling parallel processing Buffer storage Computer aided instruction Computer applications Pipelines Prefetching

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A loop allocation policy for DOACROSS loops

A loop allocation policy for DOACROSS loops

引用

international symposium on parallel and distributed processing (IPDPS)

作者： J.T. Lim A.R. Hurson K. Kavi B. Lee Computer Science and Engineering Department Pennsylvania State University University Park PA USA Computer Science and Engineering Department University of Texas Arlington Arlington TX USA Department of Electrical and Computer Engineering Oregon State University Corvallis OR USA

the dataflow model of computation, in general, and its recent direction to combine dataflow processing with control-flow processing, in particular, provide attractive alternatives to satisfy the computational demands of new applications, without experiencing the shortcomings of the traditional concurrent systems. this should motivate researchers to analyze the applicability of familiar concepts, such as scheduling and load balancing, within this new architectural framework. Effective execution of loop iterations as a means to improve performance and hardware utilization has received a great deal of attention in the past. In this paper we address the problem of scheduling/allocation of DOACROSS loops in a multithreaded dataflow environment. An extension to the staggered scheme-Cyclic staggered scheme-which produces a more balanced distribution of iterations among processors is introduced and its performance improvement in a dataflow and control-flow environment is simulated and analyzed.

关键词： Yarn parallel processing Delay Computational modeling Concurrent computing Job shop scheduling Processor scheduling Process control Hardware Switches

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An efficient file transmission algorithm for distributed computing systems

An efficient file transmission algorithm for distributed com...

引用

international symposium on parallel and distributed processing (IPDPS)

作者： D.J. Chen P.Y. Chang Y.W. Lee Computer Science and Information Engineering Department National Chiao Tung University Hsinchu Taiwan

In a distributed system, executing a program often requires the access of remote data files. An efficient data transmission strategy is thus important for real-time applications. Since data files may be replicated and their locations are transparent to the executed program, it becomes the system's responsibility to select a proper file server such that data can be transmitted in an effective way. We consider the scenario that a particular program needs several data files simultaneously for its execution. Each data file may have replicas across the network. the problem is how to find a collection of file servers and the routing paths such that the data transmission time is minimum. An exhaustive approach could of course find the optimal solution. However, it pays a high computation price. We thus propose a heuristic method. Results obtained from the proposed method are encouraging.

关键词： distributed computing File servers Routing Application software Delay Data communication Military computing Linear programming Joining processes Computer science

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An intelligent system architecture for urban traffic control applications

An intelligent system architecture for urban traffic control...

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international symposium on parallel and distributed processing (IPDPS)

作者： M.I. Patel N. Ranganathan Department of Computer Science and Engineering University of South Florida Tampa FL USA

this paper describes an intelligent system architecture for urban traffic control which integrates a neural network and an expert system on silicon. the intelligent decision making system consists of a backpropagation based neural network for adaptive learning and a rule-based fuzzy expert system for decision making. Both the neural network and the expert system are implemented as linear systolic arrays. thus, the entire system can be realized in VLSI with a few basic cells. the architecture exploits the principles of pipelining and parallelism to the maximum possible extent in order to achieve high speed and throughput. the effectiveness of the proposed system is illustrated by mapping two application problems: (i) adaptive traffic light control and (ii) congestion detection and avoidance in urban traffic control. the proposed hardware can yield a real-time decision every 5 ns based on a 200 MHz clock.

关键词： Intelligent systems Traffic control Neural networks Intelligent networks Expert systems Decision making Silicon Backpropagation Adaptive systems Hybrid intelligent systems

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A heterogeneous hierarchical solution to cost-efficient high performance computing

A heterogeneous hierarchical solution to cost-efficient high...

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international symposium on parallel and distributed processing (IPDPS)

作者： Z.B. Miled J.A.B. Fortes Sch. of Electr. & Comput. Eng. Purdue Univ. West Lafayette IN USA School of Electrical and Computer Engineering Purdue University West Lafayette IN USA

Two facts that suggest the desirability of a hierarchical approach to cost-effective high-performance computing are empirically established in this paper. the first fact is the temporal locality of programs with respect to the degree of parallelism. Two temporal (instruction and data) locality principles are identified and empirically established for a set of programs. the impact of this behavior is discussed with respect to the proposed heterogeneous multilevel architecture. the second fact that supports the hierarchical architecture is the cost-efficiency advantage of heterogeneous over homogeneous multiprocessor systems. An initial performance analysis is presented which quantifies this fact for the proposed heterogeneous hierarchical organization. the proposed multilevel processor configuration uses fast and costly resources sparingly to reduce sequential and low parallelism bottlenecks. the resulting organization tries to balance cost, speed and parallelism granularity.

关键词： High performance computing parallel processing Concurrent computing Costs Bridges Multiprocessing systems Research and development Application software Computer applications Environmental economics

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Sorting N items using a p-sorter in optimal time

Sorting N items using a p-sorter in optimal time

引用

international symposium on parallel and distributed processing (IPDPS)

作者： S. Olarin S.Q. Zheng Dept. of Comput. Sci. Old Dominion Univ. Norfolk VA USA Department of Computer Science Louisiana State University Baton Rouge LA USA

A sorting device capable of sorting p items in constant time is called a p-sorter. It is known that the task of sorting N items using a p-sorter requires at least /spl Omega/ (N log N/p log p) applications of the p-sorter. this bound is tight: there exist algorithms that use O (N log N/p log p) calls to the p-sorter to sort N items. However, there is no known implementable algorithm that can sort N items in O(N log N/p log p) time using a p-sorter. the main contribution of this paper is to propose a simple VLSI architecture and to show that in our architecture N items can be sorted in O(N log N/p log p) calls to the p-sorter, while enforcing conflict-free memory accesses. An important feature of our design is that the total additional VLSI area for hardware, other than the memory for data and the p-sorter, is kept to a minimum.

关键词： Sorting Very large scale integration Computer architecture Computer science Semiconductor device measurement Application software Hardware parallel algorithms parallel processing parallel architectures

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Efficient algorithms for block-cyclic redistribution of arrays

Efficient algorithms for block-cyclic redistribution of arra...

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international symposium on parallel and distributed processing (IPDPS)

作者： Young Won Lim P.B. Bhat V.K. Prasanna Department of EE-Systems University of Southern California Los Angeles CA USA

We present new algorithmic techniques for a classical research problem, runtime redistribution of an array from one block-cyclic layout to another. Our methodology for reducing communication overheads is based on a generalized circulant matrix formalism. Using this formalism, we derive direct, indirect, and hybrid communication schedules for the cyclic redistribution problem when the block size changes by an integer factor K. We have also developed formulae to estimate the timing performance of each of these schedules for a given parallel machine and redistribution problem. In our indirect communication schedule, blocks are moved from a source processor to a destination processor through intermediate "relay" processors. this reduces the number of communication steps by an order of magnitude, in comparison with previous approaches. this algorithm performs cyclic(x) to cyclic(Kx) redistribution on P processors in [log/sub 2/K]+2 steps. Implementations of these algorithms on the Cray T3D and on the IBM SP-2 show superior performance over previous approaches. Since our algorithms are developed using MPI, they can be easily ported to different application environments. Our techniques can be used in the design of scalable redistribution libraries, in efficient implementations of the REDISTRIBUTE directive of HPF and in developing parallel algorithms for various HPC applications.

关键词： Signal processing algorithms Processor scheduling parallel machines Algorithm design and analysis Libraries parallel algorithms High performance computing Program processors Programming profession Search problems

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Scheduling from the perspective of the application 96

Scheduling from the perspective of the application

引用

international symposium on High Performance distributed Computing

作者： F. Berman R. Wolski Department of Computer Science and Engineering University of California San Diego La Jolla CA USA University of California San Diego La Jolla CA US Dept. of Comput. Sci. & Eng. California Univ. San Diego La Jolla CA USA

ISBN: (纸本)9780818675829

Metacomputing is the aggregation of distributed and high-performance resources on coordinated networks. With careful scheduling, resource-intensive applications can be implemented efficiently on metacomputing systems at the sizes of interest to developers and users. In this paper, we focus on the problem of scheduling applications on metacomputing systems. We introduce the concept of application-centric scheduling in which everything about the system is evaluated in terms of its impact on the application. Application-centric scheduling is used by virtually all metacomputer programmers to achieve performance on metacomputing systems. We describe two successful metacomputing applications to illustrate this approach, and describe AppLeS (Application-Level Scheduling) agents which generalize the application-centric scheduling approach. Finally, we show preliminary results which compare AppLeS-derived schedules with conventional strip and blocked schedules for a 2D Jacobi code.

关键词： Metacomputing Processor scheduling Concurrent computing Application software parallel processing High performance computing Strips Jacobian matrices Computer networks Contracts

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Performance comparison of desktop multiprocessing and workstation cluster computing 96

Performance comparison of desktop multiprocessing and workst...

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international symposium on High Performance distributed Computing

作者： P.E. Crandall E.V. Sumithasri M.A. Clement Computer Science & Engineering University of Connecticut Storrs CT USA Computer Science Department Brigham Young University Provo UT USA

ISBN: (纸本)9780818675829

the paper describes initial findings regarding the performance tradeoffs between cluster computing where the participating processors are independent machines connected by a high speed switch and desktop multiprocessing where the processors reside within a single workstation and share a common memory. While interprocessor communication time has typically been cited as the limiting force on performance in the cluster, bus and memory contention have had similar effects in shared memory systems. the advent of high speed interconnects and improved bus and memory access speeds have enhanced the performance curves of both platforms. We present comparisons of the execution times of three applications with varying levels of data dependencies-numerical integration, matrix multiplication, and Jacobi iteration across three environments: the PVM distributed memory model, the PVM shared memory model, and the Solaris threads package.

关键词： Workstations Switches parallel processing Computer science High performance computing Communication switching Jacobian matrices Concurrent computing distributed computing Costs

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