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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

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Exploiting Box Expansion and Grid Partitioning for parallel FPGA Routing

Exploiting Box Expansion and Grid Partitioning for Parallel ...

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Annual ieee symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Minghua Shen Guojie Luo Nong Xiao School of Data and Computer Science Sun Yat-sen University China Center for Energy-efficient Computing and Applications Peking University China

FPGA is reconfigurable architecture able to implement a good trade-off in terms of energy, performance, and flexibility. However, the main drawback in using FPGAs is their very long routing time. Multi-core processors are now ubiquitous, making parallelism an increasingly attractive direction to accelerate the routing time. In this paper, we propose a task-level distributed parallel router that exploits conflict-aware box expansion and equal-sized grid partitioning for parallel FPGA routing. In box expansion, we adopt net bounding box to limit the search space of routing and based on current congestion state among nets, we design conflict-aware box expansion to optimize the serial routing time and provide more non-conflicting nets to obtain significant parallelism. In grid partitioning, we employ equal-sized grid to partition the overall routing region, where the nets in same grid are routed in serial and the grids are processed in parallel. Specifically, the nets distributed in multiple grids can be used to balance the workloads among processor cores. Experiments show that the parallel implementation scales to an average speedup of about 21 × using 32 processor cores compared to state-of-the-art VPR router.

关键词： Routing Field programmable gate arrays parallel processing Task analysis Servers Computer science Electronic mail

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parallel retrograde analysis on different architecture

Parallel retrograde analysis on different architecture

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international symposium on High Performance distributed Computing

作者： Ren Wu D.F. Beal HP Laboratories Hewlett Packard Company USA Department of Computer Science Queen Mary & Westfield College London University UK

Retrograde analysis is an efficient exhaustive search method. It is a powerful tool that can be used in solving problems where end states have known values but starting states do not. It has been widely used to solve mathematically-precise games such as chess endgames, and is potentially usable in energy-minimization problems. With increasing computing power, both in speed and storage capacity, retrograde analysis will become more and more useful. this paper looks at successful applications to games, the challenges ahead and the modifications that are required to utilize distributed hardware. the power and the usefulness of retrograde analysis are still limited by the computing resources one has access to. Today, the best sequential retrograde algorithms are capable of solving problems with about 10/sup 9/ states in a few hours on a standard personal computer. Bigger problems need more powerful computers, or take much longer to solve, or are simply out of the reach of today's technologies. Introducing parallelism to retrograde analysis is a natural way to attack the bigger problems. there are today three main architectures available for doing parallel retrograde analysis, namely symmetric multiprocessor (SMP) systems, high-speed network-based distributed systems and Internet-based distributed systems. In this paper, we discuss some of the key issues in doing parallel retrograde analysis on these different architectures. Technical challenges are addressed in detail, as well as some examples and proposals. these examples and proposals are drawn from various board games, but the ideas can be applied to other problem domains.

关键词： Computer architecture Proposals Laboratories Search methods Hardware Microcomputers parallel processing Multiprocessing systems High-speed networks IP networks

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Improving Availability and Scalability for RDMA Load Balancing with In-network Reordering

Improving Availability and Scalability for RDMA Load Balanci...

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international symposium on parallel and distributed processing with applications, ISPA

作者： Jinbin Hu Ruiqian Li Shuying Rao Jin Wang Changsha University of Science and Technology Changsha China Hunan University of Science and Technology Xiangtan China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

Remote Direct Memory Access (RDMA) is widely deployed in datacenter networks (DCNs) due to its ultra-low latency, high throughput, and low CPU overhead. Since RDMA is sensitive to out-of-order packets, the previous load balancing schemes designed based on TCP do not work well in RDMA networks. Recently proposed load balancing schemes focus on solving packet reordering within the network. However, the existing solutions cannot be extended in practice because the required queues far exceed common switch capabilities. In this paper, we propose a scalable and efficient load balancing called SELB to improve availability and scalability. SELB employs a clustering algorithm to categorize equal-cost paths and then reroutes traffic to the same cluster parallel paths to reduce the degree of out-of-order and improve queue utilization. the NS-3 simulation results demonstrate that SELB reduces the average flow completion time (FCT) and the 99th percentile FCT by up to 33% and 21%, respectively, compared to the state-of-the-art load balancing schemes.

关键词： Out of order distributed processing Scalability Simulation Clustering algorithms Switches Load management throughput Classification algorithms

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A Simplified and Accurate Model of Power-Performance Efficiency on Emergent GPU Architectures

A Simplified and Accurate Model of Power-Performance Efficie...

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international symposium on parallel and distributed processing (IPDPS)

作者： Shuaiwen Song Chunyi Su Barry Rountree Kirk W. Cameron Virginia Technology Blacksburg VA USA Lawrence Livermore National Laboratory Livermore CA USA

ISBN: (纸本)9781467360661

Emergent heterogeneous systems must be optimized for both power and performance at exascale. Massive parallelism combined with complex memory hierarchies form a barrier to efficient application and architecture design. these challenges are exacerbated with GPUs as parallelism increases orders of magnitude and power consumption can easily double. Models have been proposed to isolate power and performance bottlenecks and identify their root causes. However, no current models combine simplicity, accuracy, and support for emergent GPU architectures (e.g. NVIDIA Fermi). We combine hardware performance counter data with machine learning and advanced analytics to model power-performance efficiency for modern GPU-based systems. Our performance counter based approach is simpler than previous approaches and does not require detailed understanding of the underlying architecture. the resulting model is accurate for predicting power (within 2.1%) and performance (within 6.7%) for application kernels on modern GPUs. Our model can identify power-performance bottlenecks and their root causes for various complex computation and memory access patterns (e.g. global, shared, texture). We measure the accuracy of our power and performance models on a NVIDIA Fermi C2075 GPU for more than a dozen CUDA applications. We show our power model is more accurate and robust than the best available GPU power models - multiple linear regression models MLR and MLR+. We demonstrate how to use our models to identify power-performance bottlenecks and suggest optimization strategies for high-performance codes such as GEM, a biomolecular electrostatic analysis application. We verify our power-performance model is accurate on clusters of NVIDIA Fermi M2090s and useful for suggesting optimal runtime configurations on the Keeneland supercomputer at Georgia Tech.

关键词： Graphics processing units Radiation detectors Training Predictive models Kernel Runtime Adaptation models

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Efficient reconfigurable architectures of generic cyclic convolution

Efficient reconfigurable architectures of generic cyclic con...

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ieee international symposium on Consumer Electronics (ISCE)

作者： B. Krill A. Amira Nanotechnology and Integrated Bio-Engineering Centre (NIBEC) Faculty of Computing and Engineering University of Ulster Belfast Antrim UK

this paper presents the design and implementation of a generic cyclic convolution architecture for imaging applications on field programmable gate array (FPGA). Two main architectures are implemented. A parallel architecture using distributed arithmetic (DA) and a sequential implementation using FPGA digital signal processor (DSP) resources were implemented using VHSIC hardware description language (VHDL) and synthesised on Xilinx Virtex-5 FPGA. Experimental results, comparisons and performance analysis of the area, power consumption, maximum frequency and throughput are analysed in this paper. Also a performance comparison between a software implementation and the FPGA implementation has been done. Finally, an evaluation of the generic cyclic convolution has been carried out and reveals a significant trade-off of throughput and maximum frequency.

关键词： Convolution Field programmable gate arrays Computer architecture Digital signal processing throughput Read only memory Mathematical model

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Enhanced null message algorithm for hybrid parallel simulation systems with large disparity in time step

Enhanced null message algorithm for hybrid parallel simulati...

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international Workshop/symposium on distributed Simulation and Real-Time applications (DS-RT)

作者： Bin Wang Yanlong Zhai Zishuo Wang Han Zhang Duzheng Qing Beijing Engineering Research Center of Massive Language Information Processing and Cloud Computing Applications Bijing Institute of Technology Beijing China Science and Technology on Special System Simulation Laboratory Beijing Simulation Center China

ISBN: (纸本)9781509035069

Modeling and simulation has received significant attention over the years for its ability to understand and transform real world systems. With the increasing of complexity and scale of the simulated systems, more computational power is required. parallel discrete event simulation(PDES) is an important technology to integrate parallel computing into modeling and simulation. Time synchronization algorithm is the core of PDES, which determines the correctness and efficiency of the simulation. Traditional conservative synchronization algorithms, such as Chandy-Misra-Bryant(CMB) null message algorithm, use null message to synchronize the state and avoid deadlock among logical processes(LPs). But hybrid simulation systems contains both continuous models and discrete models, continuously changing states is typically modeled using time steps in hybrid simulation system. therefore, hybrid systems with large disparity in time step are very common in real simulation systems. However, current conservative synchronization algorithm has not been fully investigated for this type of simulation systems and will generate massive synchronization messages. this paper proposed an enhanced null message algorithm for hybrid simulation systems with large disparity in time step. It extended the CMB algorithm by adding simulation time in null message request messages. this could significantly reduce the number of synchronization messages. Experimental results showed that our synchronization algorithm outperforms the CMB algorithm by reducing a great number of synchronization messages.

关键词： Synchronization Computational modeling Atmospheric modeling Adaptation models System recovery Ports (Computers) Complex systems

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Performance comparison of desktop multiprocessing and workstation cluster computing 96

Performance comparison of desktop multiprocessing and workst...

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international symposium on High Performance distributed Computing

作者： P.E. Crandall E.V. Sumithasri M.A. Clement Computer Science & Engineering University of Connecticut Storrs CT USA Computer Science Department Brigham Young University Provo UT USA

ISBN: (纸本)9780818675829

the paper describes initial findings regarding the performance tradeoffs between cluster computing where the participating processors are independent machines connected by a high speed switch and desktop multiprocessing where the processors reside within a single workstation and share a common memory. While interprocessor communication time has typically been cited as the limiting force on performance in the cluster, bus and memory contention have had similar effects in shared memory systems. the advent of high speed interconnects and improved bus and memory access speeds have enhanced the performance curves of both platforms. We present comparisons of the execution times of three applications with varying levels of data dependencies-numerical integration, matrix multiplication, and Jacobi iteration across three environments: the PVM distributed memory model, the PVM shared memory model, and the Solaris threads package.

关键词： Workstations Switches parallel processing Computer science High performance computing Communication switching Jacobian matrices Concurrent computing distributed computing Costs

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Scheduling based on the impact over process communication of parallel applications

Scheduling based on the impact over process communication of...

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ieee international symposium on High Performance Computing Systems and applications (HPCS)

作者： R.P. Ishii R.F. de Mello L.J. Senger M.J. Santana R.H.C. Santana Instituto de Ciências Matemáticas e de Computação Universidade de Sáo Paulo Sao Paulo Brazil

this paper presents a new model for the evaluation of the impacts on processing operations resulting from the communication among processes. the model quantifies the traffic volume imposed on the communication network by means of the latency parameters and the overhead. Such parameters represent the load that each process imposes over the network and the delay on the CPU, as a consequence of the network operations. the delay is represented on the model by means of metric measurements slowdown. the equations that quantify the costs involved in the processing operation and message exchange are defined. In the same way, equations to determine the maximum network bandwidth are used on the decision-making scheduling. the proposed model uses a constant that delimitates the communication network maximum allowed usage, this constant defines two possible scheduling techniques: group scheduling or through communication network. Such techniques are incorporated to the DPWP policy, generating an extension of this policy. Results confirm the performance enhancement of parallel applications.

关键词： Processor scheduling Communication networks Delay Bandwidth Resource management Equations Decision making distributed computing Weather forecasting Electronic mail

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An auto-tuning approach for optimizing base operators for non-destructive testing applications on heterogeneous multi-core architectures

An auto-tuning approach for optimizing base operators for no...

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international symposium on Object-Oriented Real-Time distributed Computing

作者： thomas Heller Dietmar Fey Markus Rehak Friedrich-Alexander Universität Erlangen-Nurnberg Erlangen Germany Development Center X-Ray Technology Fraunhofer Institute for Integrated Circuits IIS Furth Germany

the field of non-destructive testing imposes rising performance requirements related to the compute resources necessary to satisfy application needs. the creation of scalable applications in that field, which efficiently utilize today's mostly heterogeneous compute resources has proven to be complicated. In order to allow domain experts coming from a materials science background, to exploit modern heterogenous computing architectures, new classes of frameworks for efficient applications need to be developed. this paper proposes a new framework to develop efficient operators and operator chains for applications in the field of non-destructive testing, based on a self-organizing autotuning approach. the framework provides a C++ Interface to define base operators and implements an Embedded Domain Specific Language (EDSL) using C++ Expression Templates (ETs) which allows a succinct definition of an Operator Chain. the framework applies various kinds of optimizations by utilizing C++ Template Metaprogramming techniques. these optimizations include feedback based auto-tuning and auto-parallelization of the resulting Pipeline based on the advanced dataflow and future's techniques provided by the High Performance ParalleX (HPX), a general purpose parallel C++ runtime system.

关键词： Optimization Pipelines Testing Hardware Abstracts Multicore processing

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MPISE: Symbolic Execution of MPI Programs

MPISE: Symbolic Execution of MPI Programs

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ieee international Symposim on High Assurance Systems Engineering

作者： Xianjin Fu Zhenbang Chen Yufeng Zhang Chun Huang Wei Dong Ji Wang College of Computer National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9781479981120

Message Passing Interfaces (MPI) plays an important role in parallel computing. Many parallel applications are implemented as MPI programs. the existing methods of bug detection for MPI programs have the shortage of providing both input and non-determinism coverage, leading to missed bugs. In this paper, we employ symbolic execution to ensure the input coverage, and propose an on-the-fly schedule algorithm to reduce the interleaving explorations for non-determinism coverage, while ensuring the soundness and completeness. We have implemented our approach as a tool, called MPISE, which can automatically detect the deadlock and runtime bugs in MPI programs. the results of the experiments on benchmark programs and real world MPI programs indicate that MPISE finds bugs effectively and efficiently. In addition, our tool also provides diagnostic information and replay mechanism to help understand bugs.

关键词： Computer bugs System recovery Switches Synchronization Runtime Testing Scheduling

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