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检索条件"任意字段=13th IEEE International Symposium on Parallel and Distributed Processing with Applications"

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A Discrete Data Dividing Approach for Erasure-Code-Based Storage applications

A Discrete Data Dividing Approach for Erasure-Code-Based Sto...

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2014 ieee 8th international symposium on Service Oriented System Engineering

作者： Weidong Sun Yijie Wang Yongquan Fu Xiaoqiang Pei Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha Hunan P. R. China

Erasure codes are promising for improving the reliability of the storage system due to its space efficiency compared to the replication methods. Traditional erasure codes split data into equalsized data blocks and encode strips in different data blocks. this brings heavy repairing traffic when clients read parts of the data, since most strips read for repairing are not in the expected blocks. this paper proposes a novel discrete data dividing method to completely avoid this problem. the key idea is to encode strips from the same data block. We could see that for repairing failed blocks, the strips to be read are either in the same data block with corrupted strips or from the encoded strips. therefore, no data is wasted. We design and implement this data layout into a HDFS-like storage system. Experiments over a small-scale testbed shows that the proposed discrete data divided method avoids downloading data blocks that are not needed for clients during the repairing operations.

关键词： Strips Decoding Encoding distributed databases Writing Reliability Magnetic heads

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I/O requirements of scientific applications: an evolutionary view 96

I/O requirements of scientific applications: an evolutionary...

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international symposium on High Performance distributed Computing

作者： E. Smirni R.A. Aydt A.A. Chien D.A. Reed Department of Computer Science University of Illinois Urbana IL USA

ISBN: (纸本)9780818675829

the modest I/O configurations and file system limitations of many current high-performance systems preclude solution of problems with large I/O needs. I/O hardware and file system parallelism is the key to achieving high performance. We analyze the I/O behavior of several versions of two scientific applications on the Intel Paragon XP/S. the versions involve incremental application code enhancements across multiple releases of the operating system. Studying the evolution of I/O access patterns underscores the interplay between application access patterns and file system features. Our results show that both small and large request sizes are common, that at present, application developers must manually aggregate small requests to obtain high disk transfer rates, that concurrent file accesses are frequent, and that appropriate matching of the application access pattern and the file system access mode can significantly increase application I/O performance. Based on these results, we describe a set of file system design principles.

关键词： Hardware File systems parallel processing Application software Contracts Computer science Operating systems Aggregates Pattern matching Software performance

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Performance Comparision of TPU, GPU, CPU on Google Colaboratory Over distributed Deep Learning

Performance Comparision of TPU, GPU, CPU on Google Colaborat...

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ieee international symposium on Embedded Multicore Socs (MCSoC)

作者： Haklin Kimm Incheon Paik Hanke Kimm East Stroudsburg University East Stroudsburg PA USA School of Computer Science and Engineering University of Aizu Aizu-Wakamatsu City Fukushima Japan Stony Brook University Stony Brook NY USA

ISBN: (纸本)9781728187525

Deep Learning models need massive amounts compute powers and tend to improve performance running on special purpose processors accelerators designed to speed up compute-intensive applications. the accelerators like Tensor processing Units (TPUs) and Graphics processing Units (GPUs) are widely used as deep learning hardware platforms which can often achieve better performance than CPUs, with their massive parallel execution resources and high memory bandwidth. Google Colaboratory known as Colab is a cloud service based on Jupyter Notebook that allows the users to write and execute mostly Python in a browser and admits free access to TPUs and GPUs without extra configuration need, which are widely available cloud hardware platforms. In this paper, we present a through comparison of the hardware platforms on Google Colab that is benchmarked with distributed Bidirectional Long Short-Term Memory (dBLSTM) models upon the number of layers, the number of units each layer, and the numbers of input and output units the datasets. Human Activity Recognition (HAR) data from UCI machine-learning library have been applied to the proposed distributed bidirectional LSTM model to find the performance, strengths, bottlenecks of the hardware platforms of TPU, GPU and CPU upon hyperparameters, execution time, and evaluation metrics: accuracy, precision, recall and F1 score.

关键词： Deep learning Measurement Training Runtime Tensors Graphics processing units Benchmark testing

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Collective caching: application-aware client-side file caching 05

Collective caching: application-aware client-side file cachi...

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international symposium on High Performance distributed Computing

作者： Wei-keng Liao K. Coloma A. Choudhary L. Ward E. Russell S. Tideman Electrical and Computer Engineering Department Northwestern University USA Scalable Computing Systems Department Sandia National Laboratories

ISBN: (纸本)9780780390379

parallel file subsystems in today's high-performance computers adopt many I/O optimization strategies that were designed for distributed systems. these strategies, for instance client-side file caching, treat each I/O request process independently, due to the consideration that clients are unlikely related with each other in a distributed environment. However, it is inadequate to apply such strategies directly in the high-performance computers where most of the I/O requests come from the processes that work on the same parallel applications. We believe that client-side caching could perform more effectively if the caching subsystem is aware of the process scope of an application and regards all the application processes as a single client. In this paper, we propose the idea of "collective caching" which coordinates the application processes to manage cache data and achieve cache coherence without involving the I/O servers. To demonstrate this idea, we implemented a collective caching subsystem at user space as a library, which can be incorporated into any message passing interface implementation to increase its portability. the performance evaluation is presented with three I/O benchmarks on an IBM SP using its native parallel file system, GPFS. Our results show significant performance enhancement obtained by collective caching over the traditional approaches.

关键词： Concurrent computing Application software File servers File systems Laboratories Message passing parallel processing Data structures Libraries

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Using Semantic Information to Guide Efficient parallel I/O on Clusters 02

Using Semantic Information to Guide Efficient Parallel I/O o...

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Proceedings of the 11th ieee international symposium on High Performance distributed Computing

作者： Martin Schulz

ISBN: (纸本)9780769516868

Despite the large I/O capabilities in modern cluster architectures with local disks on each node, applications mostly are not enabled to fully exploit them. this is especially problematic for data intensive applications which often suffer from low I/O performance. As one solution for this problem, a Distribution I/O Management (DIOM) system has been developed to manage a transparent distribution of data across cluster nodes and to then allow applicationsto access this data purely from local disks. In order to be effective, however, this distribution process requires semantic information about both the application and the input data. this work therefore extends DIOM to include independent specifications for both data formats and application I/O patterns and thereby decouples them. this work is driven by an application from nuclear medical imaging, the reconstruction of PET images, for which DIOM has provento be an adequate solution enabling truly scalable I/O and thereby improving the overall application performance.

关键词： Medical Image processing parallel and distributed I/O distributed Data Management Cluster Middleware Data Intensive applications

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A Memory Access Pattern-Based Program Profiling System for Dynamic parallelism Prediction

A Memory Access Pattern-Based Program Profiling System for D...

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ieee international Conference on Trust, Security and Privacy in Computing and Communications

作者： Zijun Han Guangzhi Qu Dona Burkard Kelvin Dobbins Comput. Sci. & Eng. Dept. Oakland Univ. Rochester MI USA Res. & Innovation Center Ford Motor Co. Dearbon MI USA

ISBN: (纸本)9781509032068

parallel computing is the simultaneous use of multiple computer resources to solve a computational problem. In order to automatically execute a sequential program so that inherent parallelism could utilize the underlying multi-core platforms, program profiling is necessary to learn the control and dataflow dependency which is critical for predicting the parallelization feasibility and finding parallelism solutions. In literature, algorithms and tools have been designed for either dynamic or static program analysis in order to increase the accuracy and performance in discovering all aspects of the target program. However, memory and runtime overhead remain two challenge problems for program profiling. In this work, based on the PIN framework, we have designed and implemented a memory access pattern-based program profiling system for sequential program parallelization prediction. Validation results on seven SPEC 2006 benchmark programs show the effectiveness of proposed system on both memory usage and cpu time for target program dynamic profiling.

关键词： parallel processing History Memory management Engines Runtime Pins Heuristic algorithms parallel processing (COMPUTERS) Runtime PIN Store management Heuristic algorithms Engines Bone Nails analysis programme sequential program Synclitism parallelism object programs Memory Memory CPU time

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On the Harmfulness of Redundant Batch Requests

On the Harmfulness of Redundant Batch Requests

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international symposium on High Performance distributed Computing

作者： H. Casanova Department of Information and Computer Sciences University of Hawaii Manoa USA

Most parallel computing resources are controlled by batch schedulers that place requests for computation in a queue until access to compute nodes are granted. Queue waiting times are notoriously hard to predict, making it difficult for users not only to estimate when their applications may start, but also to pick among multiple batch-scheduled resources the one that produce the shortest turnaround time. As a result, an increasing number of users resort to "redundant requests": several requests are simultaneously submitted to multiple batch schedulers on behalf of a single job; once one of these requests is granted access to compute nodes, the others are canceled. Using simulation as well as experiments with a production batch scheduler we investigate whether redundant requests are harmful in terms of (i) schedule performance and fairness, (ii) system load, and (iii) system predictability. We find that two main issues with redundant requests are load on the middleware and unfairness towards users who do not use redundant requests, which both depend on the number of users who use redundant requests and on the amount of request redundancy these users employ

关键词： Processor scheduling Concurrent computing Middleware parallel processing Resource management Computational modeling Predictive models Batch production systems State estimation Upper bound

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High Performance Non-uniform FFT on Modern X86-based Multi-core Systems

High Performance Non-uniform FFT on Modern X86-based Multi-c...

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international symposium on parallel and distributed processing (IPDPS)

作者： Dhiraj D. Kalamkar Joshua D. Trzaskoz Srinivas Sridharan Mikhail Smelyanskiy Daehyun Kim Armando Manduca Yunhong Shu Matt A. Bernstein Bharat Kaul Pradeep Dubey Parallel Computing Lab Intel Labs Bangalore KA India Mayo Clinic Minnesota Rochester MN US Parallel Computing Laboratory INTEL Research Laboratory Santa Clara CA USA Department of Physiology and Biomedical Engineering Mayo Clinic Rochester MN USA Parallel Computing Lab Intel Labs Santa Clara CA USA Department of Radiology Mayo Clinic Rochester MN USA

the Non-Uniform Fast Fourier Transform (NUFFT) is a generalization of FFT to non-equidistant samples. It has many applications which vary from medical imaging to radio astronomy to the numerical solution of partial differential equations. Despite recent advances in speeding up NUFFT on various platforms, its practical applications are still limited, due to its high computational cost, which is significantly dominated by the convolution of a signal between a non-uniform and uniform grids. the computational cost of the NUFFT is particularly detrimental in cases which require fast reconstruction times, such as iterative 3D non-Cartesian MRI reconstruction. We propose novel and highly scalable parallel algorithm for performing NUFFT on x86-based multi-core CPUs. the high performance of our algorithm relies on good SIMD utilization and high parallel efficiency. On convolution, we demonstrate on average 90% SIMD efficiency using SSE, as well up to linear scalability using a quad-socket 40-core Intel(R) Xeon(R) E7-4870 Processors based system. As a result, on dual socket Intel(R) Xeon(R) X5670 based server, our NUFFT implementation is more than 4x faster compared to the best available NUFFT3D implementation, when run on the same hardware. On Intel(R) Xeon(R) E5-2670 processor based server, our NUFFT implementation is 1.5X faster than any published NUFFT implementation today. Such speed improvement opens new usages for NUFFT. For example, iterative multi channel reconstruction of a 240×240×240 image could execute in just over 3 minutes, which is on the same order as contemporary non-iterative (and thus less-accurate) 3D NUFFT-based MRI reconstructions.

关键词： Convolution Kernel Interpolation Magnetic resonance imaging Image reconstruction Hardware Transforms

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High-order stencil computations on multicore clusters

High-order stencil computations on multicore clusters

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international symposium on parallel and distributed processing (IPDPS)

作者： Liu Peng Richard Seymour Ken-ichi Nomura Rajiv K. Kalia Aiichiro Nakano Priya Vashishta Alexander Loddoch Michael Netzband William R. Volz Chap C. Wong Collaboratory for Advanced Computing and Simulations Department of Computer Science Department of Physics & Astronomy Department of Chemical Engineering & Material Science University of Southern California Los Angeles CA USA Technical Computing Chevron ETC Houston TX USA

ISBN: (纸本)9781424437511

Stencil computation (SC) is of critical importance for broad scientific and engineering applications. However, it is a challenge to optimize complex, high-order SC on emerging clusters of multicore processors. We have developed a hierarchical SC parallelization framework that combines: (1) spatial decomposition based on message passing; (2) multithreading using critical section-free, dual representation; and (3) single-instruction multiple-data (SIMD) parallelism based on various code transformations. Our SIMD transformations include translocated statement fusion, vector composition via shuffle, and vectorized data layout reordering (e.g. matrix transpose), which are combined with traditional optimization techniques such as loop unrolling. We have thereby implemented two SCs of different characteristics-diagonally dominant, lattice Boltzmann method (LBM) for fluid flow simulation and highly off-diagonal (6-th order) finite-difference time-domain (FDTD) code for seismic wave propagation-on a Cell Broadband Engine (Cell BE) based system (a cluster of PlayStation3 consoles), a dual Intel quadcore platform, and IBM BlueGene/L and P. We have achieved high inter-node and intra-node (multithreading and SIMD) scalability for the diagonally dominant LBM: Weak-scaling parallel efficiency 0.978 on 131,072 BlueGene/P processors; strong-scaling multithreading efficiency 0.882 on 6 cores of Cell BE; and strong-scaling SIMD efficiency 0.780 using 4-element vector registers of Cell BE. Implementation of the high-order SC, on the contrary, is less efficient due to long-stride memory access and the limited size of the vector register file, which points out the need for further optimizations.

关键词： Multicore processing Multithreading Finite difference methods Time domain analysis Registers Message passing parallel processing Matrix decomposition Lattice Boltzmann methods Fluid flow

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MIC-SVM: Designing a Highly Efficient Support Vector Machine for Advanced Modern Multi-core and Many-Core Architectures

MIC-SVM: Designing a Highly Efficient Support Vector Machine...

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international symposium on parallel and distributed processing (IPDPS)

作者： Yang You Shuaiwen Leon Song Haohuan Fu Andres Marquez Maryam Mehri Dehnavi Kevin Barker Kirk W. Cameron Amanda Peters Randles Guangwen Yang Tsinghua National Laboratory for Information Science and Technology (TNList) Tsinghua University Beijing China Pacific Northwest National Lab Richland WA USA Ministry of Education Key Laboratory for Earth System Modeling Tsinghua University Beijing China MIT Computer Science and Artificial Intelligence Laboratory Cambridge MA USA Virignia Tech Blacksburg VA USA Lawrence Livermore National Lab Livermore CA USA

ISBN: (纸本)9781479938018

Support Vector Machine (SVM) has been widely used in data-mining and Big Data applications as modern commercial databases start to attach an increasing importance to the analytic capabilities. In recent years, SVM was adapted to the field of High Performance Computing for power/performance prediction, auto-tuning, and runtime scheduling. However, even at the risk of losing prediction accuracy due to insufficient runtime information, researchers can only afford to apply offline model training to avoid significant runtime training overhead. Advanced multi- and many-core architectures offer massive parallelism with complex memory hierarchies which can make runtime training possible, but form a barrier to efficient parallel SVM design. To address the challenges above, we designed and implemented MIC-SVM, a highly efficient parallel SVM for x86 based multi-core and many-core architectures, such as the Intel Ivy Bridge CPUs and Intel Xeon Phi co-processor (MIC). We propose various novel analysis methods and optimization techniques to fully utilize the multilevel parallelism provided by these architectures and serve as general optimization methods for other machine learning tools. MIC-SVM achieves 4.4-84x and 18-47x speedups against the popular LIBSVM, on MIC and Ivy Bridge CPUs respectively, for several real-world data-mining datasets. Even compared with GPUSVM, run on a top of the line NVIDIA k20x GPU, the performance of our MIC-SVM is competitive. We also conduct a cross-platform performance comparison analysis, focusing on Ivy Bridge CPUs, MIC and GPUs, and provide insights on how to select the most suitable advanced architectures for specific algorithms and input data patterns.

关键词： Support vector machines Training Computer architecture parallel processing Microwave integrated circuits Equations Bridges

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