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A Data-Oriented Method for Scheduling Dependent Tasks on High-Density Multi-GPU Systems

A Data-Oriented Method for Scheduling Dependent Tasks on Hig...

引用

ieee international Conference on High Performance Computing and Communications (HPCC)

作者： Peng Zhang Yuxiang Gao Meikang Qiu Biomedical Engineering Department Stony Brook University Stony Brook NY United States Cluster Solution Department Cray Inc. San Jose CA United States Computer Science Department Pace University New York NY United States

ISBN: (纸本)9781479989386

the rapidly-changing computer architectures, though improving the performance of computers, have been challenging the programming environments for efficiently harnessing the potential of novel architectures. In this area, though the high-density multi-GPU architecture enabled unparalleled performance advantage of dense GPUs in a single server, it has increased the difficulty for scheduling diversified and dependent tasks. We therefore propose a data-oriented method for scheduling dependent tasks for this architecture while providing its implementation. In our method, we model a parallel program as a collection of data-dependent tasks for which data dependencies are managed by an expressive matrix. Accordingly, we develop a hierarchical scheduler infrastructure for our model. In this, a top scheduler is built for querying the data-dependency matrix; three downstream schedulers for queuing computation tasks that are exclusively assigned to processor, accelerator or either; and a multitude of bottom schedulers each for providing a processing element with assigned tasks. We experiment our scheduler for examples of Strassen matrix multiplication and Cholesky matrix inversion algorithms on a computer that has 8 Tesla K40 GPUs. the results show that our method is capable of offering the efficient task parallelism while fulfilling the complex task dependencies. When advanced task-oriented schedulers have been widely designed for distributed systems, a lightweight data-driven scheduler could be an alternative and handy approach that can handle the dependent yet diversified tasks of data-intensive applications for the novel high-density multi-accelerator system.

关键词： Computer architecture Processor scheduling Computers Symmetric matrices Partitioning algorithms Runtime Graphics processing units

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Efficient compositing strategies for automotive HMI systems

Efficient compositing strategies for automotive HMI systems

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international symposium on Industrial Embedded Systems

作者： Simon Gansel Stephan Schnitzer Riccardo Cecolin Frank Dürr Kurt Rothermel Christian Maihöfer System Architecture and Platforms Department Mercedes-Benz Cars Division Daimler AG Germany Institute of Parallel and Distributed Systems University of Stuttgart Germany

the relevance of graphical functions in vehicular applications has increased significantly during the last years. Modern cars are equipped with multiple displays used by different applications such as speedometer, navigation system, or media players. the rendered output of the applications is stored in so-called off-screen buffers and then bitblitted to the screen buffer at the respective window sizes and positions. To guarantee the visibility of the potentially overlapping windows, the compositing has to match the z-order of the windows. To this end, two common compositing strategies Tile compositing and Full compositing are used, each having performance issues depending on how windows overlap. Since automotive embedded platforms are restricted in power consumption, installation space, and hardware cost, their performance is limited which effectuates the need for highly efficient bitblitting. In order to increase the performance in compositing the windows, we propose Hybrid Compositing which predicts the required bitblitting time and chooses the most efficient strategy for each pair of overlapping windows. Using various scenarios we show that our approach is faster than the other strategies. In addition, we propose CacheHybrid Compositing which reduces the CPU execution time of our approach by up to 66 %. In case of an automotive scenario we show that our optimized approach saves up to 51% bitblitting time compared to existing approaches.

关键词： Data structures Hardware Libraries Graphics Graphics processing units Predictive models Prediction algorithms

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Concepts for execution time prediction of 3D GPU rendering

Concepts for execution time prediction of 3D GPU rendering

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international symposium on Industrial Embedded Systems

作者： Stephan Schnitzer Simon Gansel Frank Dürr Kurt Rothermel Institute of Parallel and Distributed Systems University of Stuttgart Germany System Architecture and Platforms Department Daimler AG Germany

the relevance of graphical functions in vehicular applications has increased significantly during the last years. Modern cars are equipped with multiple displays used by different applications such as speedometer, navigation system, or media players. the recent trend towards hardware consolidation to reduce hardware cost, installation space, and energy consumption, causes graphical 3D applications of different safety-criticality to share a single GPU. this requires effective real-time GPU scheduling concepts to ensure safety and isolation for 3D rendering. Since current GPUs are not preemptible, a deadline-based scheduler must know the GPU execution time of GPU commands in advance. In this work, we present a novel framework to measure and predict the execution time of GPU commands using OpenGL ES 2.0. We present prediction models for the main GPU commands relevant for 3D rendering, namely, FLUSH, CLEAR, and DRAW. For the DRAW command we propose to use the 3D bounding box of the rendered model and apply the vertex shader projection to heuristically estimate the number of fragments rendered. We finally present the implementation and evaluation of our framework, which demonstrates its feasibility and shows that good prediction accuracy can be achieved. In our evaluation using realistic scenarios the absolute prediction error of the DRAW command did not exceed 260 μs.

关键词： Graphics processing units Context Rendering (computer graphics) Predictive models three-dimensional displays Real-time systems Time measurement

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Semantic Analysis of Concurrent Computing in Decentralized IoT and Robotics applications

Semantic Analysis of Concurrent Computing in Decentralized I...

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international symposium on Autonomous Decentralized Systems (ISADAS)

作者： Gennaro De Luca Yinong Chen School of Computing Informatics and Decision Systems Engineering Arizona State University Tempe AZ 85287-8809 U.S.A.

ISBN: (数字)9781728116723

ISBN: (纸本)9781728116730

As IoT and robotics applications continue to become increasingly complex and decentralized, there is an increase in the difficulty of verifying requirements such as guarantees of reliability, efficiency, and correctness of the entire system. Modern IoT and robotics research and applications employ a variety of technologies to accommodate the distribution of real world IoT devices. Many of these technologies support the orchestration of these devices with concurrent computation and workflow-based processing, e.g., Intel Service Orchestration Layer. We developed a new workflow-based programming language VIPLE (Visual IoT/Robotics Programming Language Environment), which supports the orchestration of decentralized IoT and robotics devices through concurrent computation. VIPLE has been used by many universities for teaching robotics programming, event-driven computing, service-oriented computing, and parallel computing concepts. Historically, simple single threaded applications could be verified by employing formal systems such as Hoare logic. It is difficult to verify parallel and distributed computing. In our recent research, we developed a novel system to verify the semantics and other requirements of decentralized applications written in VIPLE. this system is developed using a combination of the techniques offered in Hoare logic and Rely-Guarantee logic, and it is applied using the automatically generated Pi-Calculus representation of VIPLE applications. this paper focuses on the foundations of this system, its ability to handle concurrent computing and decentralized applications, as well as its ability to support automated verification and semantic analysis.

关键词： Computer languages Robot kinematics Internet of things Semantics Visualization Instruction sets

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PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN

PSO Optimized Design of Error Balanced Weight Stationary Sys...

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ieee international symposium on Quality Electronic Design

作者： Dantu Nandini Devi Gandi Ajay Kumar Bindu G Gowda Madhav Rao IIIT-Bangalore Bangalore India

ISBN: (数字)9798350309270

ISBN: (纸本)9798350309287

the utilization of hardware-designed approximate computing in Convolutional Neural Networks (CNNs) offers notable advantages, including accelerated performance, enhanced power efficiency, and a compact design footprint. Systolic Array (SA) architectures, optimized for matrix multiplication and convolution operations, have been extensively studied in the context of stand-alone image processing applications. However, their potential for CNN workloads has not been thoroughly assessed. SAs consist of an array of processing Elements (PEs) structured to perform product operations and accumulations. Incorporating inexact computing units in the SA introduces deviations from precise results, posing a challenge for sustaining hardware accelerator designs in CNN workloads. this paper presents a strategy for the optimal placement of both positive and negative error-distributed multipliers as PE elements to create an error-diluted SA structure. the proposed strategy to structure SA is evaluated for prewitt filter and three other filters extracted from first layer of *** paper introduces an optimization framework for selecting the most suitable PEs from a pool of positive and negative error-distributed multipliers, aiming to achieve a balance between hardware efficiency and image quality metrics. Furthermore, the framework and hardware design files are made available for further usage to the designers’ and researchers community.

关键词： Costs Computer architecture parallel processing Filtering algorithms Hardware Systolic arrays Delays

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Simulating heterogeneous models on multi-core platforms using Julia's computing language parallel potential 20

Simulating heterogeneous models on multi-core platforms usin...

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Proceedings of the ieee/ACM 24th international symposium on distributed Simulation and Real Time applications

作者： Sergey Suslov Michael Schiek Markus Robens Christian Grewing Stefan van Waasen ZEA-2 - Electronic Systems Germany

this paper addresses the questions of high-level system modelling using heterogeneous multi-tool modelling environment on parallel multi-core processing systems for simulation acceleration. the modelling technique has been applied for high-level validation of a high-precision Indoor Positioning System for Motion Analysis (IPS-MA) developed in the Central Institute Electronic Systems (ZEA-2) of the Research Center Juelich GmbH. the heterogeneous modelling environment has been built using an implementation-level model designed in Matlab Simulink, a verification model for describing the system environment using Modelica language, and Julia language for automatic generation of binding modelling environment and parallelizing the simulation of the overall model. the approach showed a good flexibility in system description and verification in the multi-instrument modelling environment and a good performance gain due to simulation parallelism.

关键词： modelica Julia computing language high level system modelling parallelized simulation distributed simulation functional verification

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Improved SPFA Algorithm Based on Cell-Like P System

Improved SPFA Algorithm Based on Cell-Like P System

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ieee international symposium on Information (IT) in Medicine and Education, ITME

作者： Hui Zhang Xiyu Liu Laisheng Xiang Business School Shandong Normal University Jinan China

Membrane computing is a fast developing natural computing field with wide applications. Cell-like P system is the one of membrane computing and it is a class of distributed and parallel computing model which is inspired from cell. then, Shortest Path Faster Algorithm is another name of queue optimization algorithm for the Bellman-Ford algorithm. It is usually used to find single-source shortest paths with negative edges and negative weights. In this paper, we use rewrite rules and dissolution rules of cell-like P system, combined with queue thresholds to improve the SPFA algorithm. We use the average distance between the point where the queue is removed and the point to be queued as the threshold. the node whose distance is less than the threshold is inserted at the beginning of the queue, otherwise, the node is inserted at the end of the queue. A directional weighted digraph is applied to prove the feasibility of the algorithm in this paper. this method takes full advantage of the parallelism of the P system and finds the shortest path with fewer steps and shorter time.

关键词： Optimization Complexity theory Business parallel processing Computational modeling Semiconductor device modeling Approximation algorithms

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Special-purposed VLIW architecture for ieee-754 quadruple precision elementary functions on FPGA

Special-purposed VLIW architecture for IEEE-754 quadruple pr...

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ieee international Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Yuanwu Lei Yong Dou Li Shen Jie Zhou Song Guo National Laboratory of Parallel & Distributed Processing National University of Defense Technology Changsha China

this work explores the feasibility to implement ieee-754-2008 standard quadruple precision (Quad) elementary functions on recent FPGAs with plenty of embedded memories and DSP blocks. First, we analysis the implementation algorithm of Quad elementary functions in detail. then, we present a special-purpose Very Large Instruction Word (VLIW) architecture for Quad elementary function (QE-Processor). the proposed processor uses a unified hardware structure, equipped with multiple basic arithmetic units, to implement various Quad algebraic and transcendental functions, in which several tradeoffs between latency and resource usage are carefully planned to avoid unbalanced resource utilization. the performance is improved through the explicitly parallel technology of custom VLIW instruction. Finally, we create a prototype of QE-Processor into Xilinx Virtex-5 and Virtex-6 FPGA chips. the experimental results show that our design can guarantee that the percentage of correct rounding is more than 99.9%. Moreover, the FPGA implementation on Virtex-6 XC6VLX760-2FF1760 FPGA, running at 220 MHz, outperforms the parallel software approach based on OpenMP running on an Intel Xeon E5620 CPU at 2.40GHz by a factor of 13X-20X for special function applications in Boost library.

关键词： Strontium Lead Random access memory System-on-a-chip Artificial intelligence

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Device View Redundancy: an adaptive low-overhead fault tolerance mechanism for many-core system

Device View Redundancy: an adaptive low-overhead fault toler...

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international Workshop on Intelligent Communication and Social Networks

作者： Wentao Jia Chunyuan Zhang Jian Fu National Key Laboratory of Parallel and Distributed Processing College of Computer National University of Defense Technology Institute for Informatics University of Amsterdam

ISBN: (纸本)9781479909735

Continued increasing of fault rate in integrate circuit makes processors more susceptible to errors, especially many-core processor. Meanwhile, most systems or applications do not need full fault coverage, which has excessive overhead. So on-demand fault tolerance is desired for these applications. In this paper, we propose an adaptive low-overhead fault tolerance mechanism for many-core system, called Device View Redundancy (DVR). It treats fault tolerance as a device that can be configured and used by application when high reliability is needed. Nevertheless, DVR exploits the idle resources for low-overhead fault tolerance, which is based on the observation that the utilization of many-core system is low due to lack of parallelism in application. Finally, the experiment shows that the performance overhead of DVR is reduced by 16% to 98% compared with full Dual Modular Redundancy (DMR).

关键词： On-demand redundancy Idle resource exploitation Dynamic coupling Low-overhead Many core system

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Hellfire: A design framework for critical embedded systems' applications

Hellfire: A design framework for critical embedded systems' ...

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ieee international symposium on Quality Electronic Design

作者： Alexandra Aguiar Sérgio J. Filho Felipe G. Magalhães thiago D. Casagrande Fabiano Hessel Faculty of Informatics PUCRS Porto Alegre Brazil

ISBN: (纸本)9781424464548

Hellfire framework (HellfireFW) presents a design flow for the design of MPSoC based critical embedded systems. Health-care electronics, security equipment and space aircraft are examples of such systems that, besides presenting typical embedded system's constraints, bring new design challenges as their restrictions are even tighter in terms of area, power consumption and high-performance in distributed computing involving real-time processing requirement. In this paper, we present the Hellfire framework, which offers an integrated tool-flow in which design space exploration (DSE), OS customization and static and dynamic application mapping are highly automated. the designer can develop embedded sequential and parallel applications while evaluating how design decisions impact in overall system behavior, in terms of static and dynamic task mapping, performance, deadline miss ratio, communication traffic and energy consumption. Results show that: i) our solution is suitable for hard real-time critical embedded systems, in terms of real-time scheduling and OS overhead; ii) an accurate analysis of critical embedded applications in terms of deadline miss ratio can be done using HellfireFW; iii) designer can better decide which architecture is more suitable for the application; iv) different HW/SW solutions by configuring both the RTOS and the HW platform can be simulated.

关键词： Embedded system Space exploration Hardware Energy consumption Real time systems Aerospace electronics Vehicle dynamics Analytical models Timing Time to market

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