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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Foreword to the special issue on 20th ieee international symposium on design and diagnostics of electronic circuits and systems (DDECS2017)

Foreword to the special issue on 20th IEEE international sym...

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作者： Zoran, Stamenkovic Ondrej, Novak Witold, Pleskacz

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QDI Binary Comparator Networks and their Application in Combinational Logic 27

QDI Binary Comparator Networks and their Application in Comb...

引用

27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Huemer, Florian TU Wien Inst Comp Engn Vienna Austria

ISBN: (纸本)9798350359343

Binary comparator networks have already been used in quasi delay-insensitive (QDI) circuit design for the construction of completion detectors. this paper demonstrates how they can also be utilized to implement a wide range of Boolean functions for combinational QDI logic blocks. designing combinational logic for QDI circuits poses several challenges because data must be processed in an encoded form (usually dual-rail) and it must be ensured that the resulting circuits do not contain hazards or orphans. these design constraints impose a considerable hardware overhead on the resulting circuits. Hence, over the years numerous design and optimization strategies have been proposed. We show that our comparator-network-based construction approach yields promising results for certain types of functions compared to other common QDI design styles.

关键词： asynchronous circuits QDI sorting networks

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Adaptive Input Normalization for Quantized Neural Networks 27

Adaptive Input Normalization for Quantized Neural Networks

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27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Schmidt, Jan Fiser, Petr Skrbek, Miroslav Czech Tech Univ Dept Digital Design Prague Czech Republic

ISBN: (纸本)9798350359343

Neural networks with quantized activation functions cannot adapt the quantization at the input of their first layer. Preprocessing is therefore required to adapt the range of input data to the quantization range. Such preprocessing usually includes an activation-wise linear transformation and is steered by the properties of the training set. We suggest to include the linear transform into the training process. Using the Jet Stream Classification task and an evaluation architecture of three quantized dense layers, we document that it improves accuracy, requires the same resources as standard preprocessing, plays a role in network pruning, and is reasonably stable with respect to initialization.

关键词： neural network data preprocessing linear transformation adaptive quantization

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the Impact of Well-Edge Proximity Effect on PMOS threshold Voltage in Various Submicron CMOS Technologies 27

The Impact of Well-Edge Proximity Effect on PMOS Threshold V...

引用

27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Grochowska, Marika Pleskacz, Witold A. Cadence Design Syst Ul Emili Plater 28 PL-00688 Warsaw Poland Warsaw Univ Technol Inst Microelect & Optoelect Ul Koszykowa 75 PL-00662 Warsaw Poland

ISBN: (纸本)9798350359343

this paper explains the background of the well-edge proximity effect (WPE) and sums up its impact on pMOS threshold voltage (V-th) in the following CMOS technologies: 65nm (bulk), 40nm (bulk) from two different vendors, 28nm (bulk and FDSOI) and 16nm (FinFET). the results clearly show that WPE cannot be ignored during layout design for any of presented technology. Fortunately, the effect of well-edge proximity is essential at 1 mu m or shorter distances. At longer distances its impact decreases almost to zero. In 40nm technology it can change threshold voltage even by 33 % for IO devices while at 16nm the change will be just 1.87%. Although the technologies are varied in transistor length and process of fabrication the WPE effect remains present.

关键词： threshold voltage

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A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks 27

A Comparison of Logic Extraction Methods in Hardware-Transla...

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27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Schmidt, Jan Fiser, Petr Skrbek, Miroslav Czech Tech Univ Dept Digital Design Prague Czech Republic

ISBN: (纸本)9798350359343

Small quantized neural networks with strong requirements on throughput and latency can be translated into logic circuits and synthesized by logic design tools. With networks having no state (memory), the circuits are combinational. To capture the function of the network (or a part of it) as a logic function, two approaches have been taken. the first one observes the inputs and outputs, while the network predicts a training set, and uses them directly as specification. the response to activation values that have not occurred in the training set remains unspecified. the other approach uses a complete set of activation values at the input of the examined part. We measured accuracy, the influence of logic minimization, and their impact on the final synthesized circuit on dense neural networks in different stages of low-magnitude pruning on the MNIST and JSC datasets. the results show that the first method can be used for functions with fan-in below 10-12 while not working against generalization. We also document the quantitative changes in quantized networks.

关键词： neural network quantization hardware logic minimization logic synthesis

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A ML-based Approach for Finding the Product Definition Space of Microelectronic Power Switches 27

A ML-based Approach for Finding the Product Definition Space...

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27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Beladi, Seyedbehnam Maurer, Linus Stricker, Jonas Pelz, Georg Univ Bundeswehr Munich Munich Germany Infineon Technol AG Munich Germany

ISBN: (纸本)9798350359343

designing power electronic switches in a timely manner is essential for a wide range of electrical applications. the challenge arises when determining the acceptable design parameters from the product definition space that lead to a functioning application. Creating a well-defined product definition space can help reduce design cycle time and minimize the risk of design failure or non-compliance with requirements. In response to this, we propose a machine learning-based framework to create this space with substantially less simulations in comparison to exhaustive and optimization-based methods. this is particularly beneficial in higher dimensions where running numerous simulations may not be feasible. We applied this approach to generic silicon power switches within a half-bridge motor drive application simulation, defining borders that closely match-above 98%-to the borders of the product definition space. In this use case, the need for simulations is reduced by a factor of five, while still meeting all operating conditions and requirements.

关键词： Product Definition Machine Learning Silicon Power MOSFET half-bridge motor drive Product design

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Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults 27

Evaluating the Reliability of Integer Multipliers With Respe...

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27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Deligiannis, Nikolaos I. Cantoro, Riccardo Reorda, Matteo Sonza Habib, S. E. D. Politecn Torino Dept Control & Comp Engn DAUIN Turin Italy Cairo Univ Dept Elect & Elect Commun Engn Giza Egypt

ISBN: (纸本)9798350359343

Arithmetic circuits form the foundation of modern digital computation, enabling us to conduct precise mathematical operations and drive the digital age. they are integral components in nearly every digital circuit, such as processors' arithmetic and logic units. Especially in safety-critical domains like automotive and aviation, the flawless operation of these circuits is of paramount importance. this paper presents a case study involving two variants of Dadda multipliers and assesses their intrinsic reliability when affected by permanent hardware faults. We conducted extensive fault injection campaigns on the circuit models under various datasets, presenting the aggregated statistical errors in the form of the mean absolute error (MAE) for each case. Specifically, we performed fault injection campaigns in which the operands are sourced from trained quantized weights of a convolutional neural network, as well as randomly generated sets of integers. the results not only reveal differences between the two circuits but also show significant variations when different datasets are used in the fault injection campaigns.

关键词： Reliability Stuck-At Fault Fault Injection Campaign Arithmetic circuits Dadda Multipliers

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PaGoRi:A Scalable Parallel Golomb-Rice Decoder 27

PaGoRi:A Scalable Parallel Golomb-Rice Decoder

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27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Vaddeboina, Mounika Kaja, Endri Yilmazer, Alper Ghosh, Uttal Ecker, Wolfgang Infineon Technol AG Neubiberg Germany Tech Univ Munich Munich Germany Rheinland Pfalz Tech Univ Kaiserslautern Landau Kaiserslautern Germany Rhein Westfal TH Aachen Aachen Germany

ISBN: (纸本)9798350359343

Deep Neural Networks (DNNs) have created opportunities to address real-world issues and expand the application of Artificial Intelligence (AI). Despite significant accuracy enhancements, DNNs pose a challenge when deployed on resource-limited edge devices commonly used in Internet of things (IoT) applications. Inference execution of the DNNs requires accessing millions of parameters responsible for most energy consumption. Compression of weights is one possible solution, but most of the existing hardware decompression units could be more efficient in terms of power, area, and energy. this paper presents a scalable version of a hardware-efficient Parallel Golomb-Rice decoder (PaGoRi). the decoder has been integrated with an industry-strength Neural Network (NN) accelerator and evaluated with three TinyML benchmarks. the PaGoRi decoder achieves optimal trade-offs between power consumption and throughput, supporting decoding capacities of four and eight weights, consuming 0.43 mW and 0.79 mW of power, respectively, while achieving a throughput of 888 MBps and 1.3 GBps, respectively.

关键词： Deep Neural Networks Internet-of-things Neural Network accelerators Golomb-Rice coding Parallel decoders

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Verifying Bio-electronic systems 26

Verifying Bio-Electronic Systems

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26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Heuer, Joseline Krenz-Baath, Rene Obermaisser, Roman Hsch Hamm Lippstadt Hamm Germany Univ Siegen Inst Embedded Syst Siegen Germany

ISBN: (纸本)9798350332773

the functional safety of implanted medical devices is of high importance. this works presents a novel concept to verify bio-electronic systems modeling the medical device in connection with the interacting biological system. the concept is applied to a setup consisting of an implanted pacemaker and an interacting organ, the human heart. the resulting model is verified with respect to relevant properties such as the reachability of hazard-related states appearing through the interaction of the bioelectronic system. In contrast to previous contributions this work demonstrates the ability to deterministicly verify bio-electronic systems containing relevant and detailed models of the interacting biological system.

关键词： Biological systems

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Performance and Error Tolerance of Stochastic Computing-based Digital Filter design 27

Performance and Error Tolerance of Stochastic Computing-base...

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27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Sengupta, Roshwin Polian, Ilia Hayes, John P. Univ Stuttgart Inst Comp Architecture & Comp Engn Stuttgart Germany Univ Michigan Comp Engn Lab Ann Arbor MI 48109 USA

ISBN: (纸本)9798350359343

Recent advances in near-sensor computing have prompted the need to design low-cost digital filters for edge devices. Stochastic computing (SC), leveraging its probabilistic bit-streams, has emerged as a compelling alternative to traditional deterministic computing for filter design. this paper examines error tolerance, area and power efficiency, and accuracy loss in SC-based digital filters. Specifically, we investigate the impact of various stochastic number generators and increased filter complexity on both FIR and IIR filters. Our results indicate that in an error-free environment, SC exhibits a 49% area advantage and a 64% power efficiency improvement, albeit with a slight loss of accuracy, compared to traditional binary implementations. Furthermore, when the input bitstreams are subject to a 2% bit-flip error rate, SC FIR and SC IIR filters have a much smaller performance degradation (1.3X and 1.9X, respectively) than comparable binary filters. In summary, this work provides useful insights into the advantages of stochastic computing in digital filter design, showcasing its robust error resilience, significant area and power efficiency gains, and trade-offs in accuracy compared to traditional binary approaches.

关键词： FIR filter IIR filter stochastic computing

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