the proceedings contain 83 papers. the topics discussed include: self-repairing and tuning reconfigurable electronics for space;safety features of SOCs: how can they be re-used?;formal verification meets robustness ch...
ISBN:
(纸本)9781424466139
the proceedings contain 83 papers. the topics discussed include: self-repairing and tuning reconfigurable electronics for space;safety features of SOCs: how can they be re-used?;formal verification meets robustness checking - techniques and challenges;ensuring high testability without degrading security;advanced embedded memory testing: reducing the defect per million level at lower test cost;automated simulation-based verification of power requirements for systems-on-chips;noise determination of a current conveyor in an inverting voltage amplifier configuration;utilizing the bulk-driven technique in analog circuit design;instruction reliability analysis for embedded processors;self-adaptive mechanism for cache memory reliability improvement;reconfigurable hardware objects for image processing on FPGAS;modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs;and the novel approach to wideband RFIC receivers in standard CMOS process.
the proceedings contain 63 papers. the topics discussed include: hardware-software co-visualization: developing systems in the holodeck;approximate computing for energy-efficient error-resilient multimedia systems;int...
ISBN:
(纸本)9781467361361
the proceedings contain 63 papers. the topics discussed include: hardware-software co-visualization: developing systems in the holodeck;approximate computing for energy-efficient error-resilient multimedia systems;interpolation-based model checking for efficient incremental analysis of software;cross-layer resilient system design;hardware acceleration in computer networks;fault-based attacks on cryptographic hardware;exploring processor parallelism: estimation methods and optimization strategies;on design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems;on the on-line functional test of the reorder buffer memory in superscalar processors;fault collapsing of multi-conditional faults;and efficient automated speedpath debugging.
the proceedings contain 78 papers. the topics discussed include: 3D integration: opportunities, design challenges and approaches;asynchronous circuit design: from basics to practical applications;automated synthesis a...
ISBN:
(纸本)9781467311854
the proceedings contain 78 papers. the topics discussed include: 3D integration: opportunities, design challenges and approaches;asynchronous circuit design: from basics to practical applications;automated synthesis and design error repair of systems;fault management in an ieee PI687 (IJTAG) environment;design methodology for fault tolerant ASICs;selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown;synthesis of petri nets into FPGA with operation flexible memories;an evaluation of the application dependent FPGA test method;AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems;improving the iterative power of resynthesis;NAND/NOR gate polymorphism in low temperature environment;and current sensing completion detection in dual-rail asynchronous systems.
the proceedings contain 59 papers. the topics discussed include: TPG for crosstalk faults between on-chip aggressor and victim using genetic algorithms;LFSR reseeding based test compression respecting different contro...
ISBN:
(纸本)9781479967803
the proceedings contain 59 papers. the topics discussed include: TPG for crosstalk faults between on-chip aggressor and victim using genetic algorithms;LFSR reseeding based test compression respecting different controllability of decompressor outputs;compiler-centred microprocessor design (CoMet) - from C-code to a VHDL model of an ASIP;a design for the 178-MHz WXGA 30-fps optical flow processor based on the HOE algorithm;design-for-diagnosis architecture for power switches;a novel compact dual-band bandpass waveguide filter;fully differential difference amplifier for low-noise applications;SystemC-based loose models for simulation speed-up by abstraction of RTL IP cores;NoCDepend: a flexible and scalable dependability technique for 3D networks-on-chip;a synchronous mirror delay with duty-cycle tunable technology;triangular modulation using switched-capacitor scheme for spread-spectrum clocking;and application of evolutionary algorithms for regression suites optimization.
the proceedings contain 45 papers. the topics discussed include: system-level reliability evaluation through cache-aware software-based fault injection;a fault injection platform for the analysis of soft error effects...
ISBN:
(纸本)9781509024674
the proceedings contain 45 papers. the topics discussed include: system-level reliability evaluation through cache-aware software-based fault injection;a fault injection platform for the analysis of soft error effects in FPGA soft processors;comparison of gate-driven and bulk-driven current mirror topologies;multi-objective BDD optimization for RRAM based circuit design;FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization;a general approach for comparing metastable behavior of digital CMOS gates;hardware implementation of a medium access control layer for industrial wireless LAN;comparative BTI analysis for various sense amplifier designs;impedance calculation based method for ac fault analysis of mixed-signal circuits;co-design of CML IO and interposer channel for low area and power signaling;bioSoC: highly integrated system-on-chip for health monitoring;an effective approach for functional test programs compaction;sequential test decompressors with fast variable wide spreading;built-in self-repair architecture generator for digital cores;and early-stage verification of power-management specification in low-power systemsdesign.
the proceedings contain 65 papers. the topics discussed include: automatic architecture exploration of massively parallel MPSoCs for modern cyber-physical systems;design and testing of integrated circuit of pixel arch...
ISBN:
(纸本)9781479945580
the proceedings contain 65 papers. the topics discussed include: automatic architecture exploration of massively parallel MPSoCs for modern cyber-physical systems;design and testing of integrated circuit of pixel architecture for fast x-ray imaging applications;SiP design flow and 3D DRC for MEMS;studying DAC capacitor-array degradation in charge-redistribution SAR ADCs;automatically connecting hardware blocks via light-weight matching techniques;a double-path intra prediction architecture for the hardware H.265/HEVC encoder;online test vector insertion: a concurrent built-in self-testing (CBIST) approach for asynchronous logic;quality assurance in memory built-in self-test tools;fast time-parallel C-based event-driven RTL simulation;lower bounds of the size of shared structurally synthesized BDDs;BuildMaster: efficient ASIP architecture exploration through compilation and simulation result caching;and analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulators.
Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volum...
Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to ieee Copyrights Manager, ieee Operations Center, 445 Hoes Lane, Piscataway, NJ 08854. All rights reserved. Copyright (c) 2013 by ieee. ieee Catalog Number: CFP13DDE-ART. ISBN: 978-1-4673-6136-1.
Assessing the structural similarity of different implementations of logic functions is of importance in many areas of digital design, such as iterative resynthesis, engineering change order (ECO) based design, design ...
详细信息
ISBN:
(数字)9798331528010
ISBN:
(纸本)9798331528027
Assessing the structural similarity of different implementations of logic functions is of importance in many areas of digital design, such as iterative resynthesis, engineering change order (ECO) based design, design of reliable redundant systems (duplex, TMR), etc. In general, numerous metrics exist that describe such similarity, mostly based on its intended application. In this paper, we introduce a novel metric based on a calculation of the functional equivalence of subcircuits. As this approach requires repeated calls of time-consuming functional equivalence checking, we propose a linear-time approximation of this method based on signal controllability calculation. these two approaches are compared to the state-of-the-art fault detection-based design diversity estimation technique and applied to assess the fault-security capabilities of duplex systems.
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