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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis

A Parameterizable Chisel Generator of Numerically Controlled...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Vukan D. Damnjanović Marija L. Petrović Vladimir M. Milovanović Faculty of Engineering University of Kragujevac Sestre Janjić 6 Kragujevac Serbia NOVELIC Veljka Dugoševića Belgrade Serbia

Numerically controlled oscillators (NCOs) as part of direct digital synthesizers (DDS) are important components in many digital communication subsystems, such as various digital modulation and demodulation schemes, up and down converters, radar, sonar and laser appliances, etc. the vast number of their beneficial characteristics is what makes NCOs so widely used. Taking this into account, a parameterizable generator of numerically controlled oscillators is implemented using Chisel hardware design language. the proposed generator provides a broad range of parameter configurations, such as input and output data types and widths, the number of different output samples, optional use of spur-reducing techniques or different input interfaces, just to name a few. Numerous generated instances have been tested in software simulations and mapped and tested onto a commercial FPGA platform. Obtained results proved that a generator of this kind can legitimately be compared with custom designed NCO modules, both in terms of performance and resource utilization.

关键词： Laser radar design methodology Synthesizers Sonar applications Generators Hardware Space exploration

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Approximate Multipliers for Optimal Utilization of FPGA Resources

Approximate Multipliers for Optimal Utilization of FPGA Reso...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Christoph Niemann Michael Rethfeldt Dirk Timmermann Institute of Applied Microelectronics and Computer Engineering University of Rostock Germany

Approximate or inexact arithmetic is a promising approach towards lower power consumption for applications that can tolerate a certain amount of imprecision. As human perception is limited in its precision, this applies to image and audio processing. Beyond, other applications like neuronal networks or AI processing can benefit from such arithmetic as well, as they are inherently tolerant to a certain amount of inaccuracy. One of the most critical components of arithmetic circuits regarding power, delay, and area are multipliers. Various sophisticated approaches towards approximate multipliers are already published for ASICs. However, such ASIC approaches are under-performing in conjunction with the specific Lookup-Table (LUT)-based design of FPGAs. As FPGAs gain in importance for applications like signal processing, there is a substantial lack of approximate design methodology for FPGAs. We propose an approach towards approximate signal processing that is specifically tailored towards the LUT-based hardware of FPGAs. It allows for significant performance improvements while lowering the energy demands. While introducing an insignificant average relative error of just 0.14%, we achieve a 45.9% area reduction in terms of LUTs while decreasing the delay by 30.6% compared to the Xilinx Vivado multiplier IP core. Our proposed design is open source and available at https://***/niemann-c/approx-mult-for-fpga.

关键词： Power demand design methodology Signal processing Hardware Delays Table lookup IP networks

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Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level

Embedded Test Instrument for Intermittent Resistive Fault De...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Hassan Ebrahimi Hans G. Kerkhoff Testable Design and Test of Integrated Systems (TDT) Group University of Twente Enschede the Netherlands

ISBN: (纸本)9781665435956;9781665411813

No-fault-founds (NFFs) threaten the dependability of highly dependable systems in avionic and car industries. Moreover, they drastically increase the test and maintenance costs. One of the main causes of NFFs is intermittent resistive faults (IRFs). IRFs mostly occur due to unstable and marginal interconnections. this paper proposes a new periodic testing method to detect IRFs in interconnections at the chip and the board level. the proposed method is based on on-chip embedded test instruments (ETIs), which are scalable, fully digital, and With a low hardware cost. As a case study, a network-on-chip (NoC) infrastructure with a mesh topology has been utilised. the implementation of the testing method requires a small chip area and power consumption overheads being 3% and 2.5%, respectively. In this paper, first, IRF detection at the chip level has been investigated using simulation-based fault injections in selected interconnections of the NoC. then, the effectiveness of the proposed method at the board level has been verified by hardware-based fault injections as well as thermal cycling experiments on actual solder joints. the experimental results demonstrated that the on-chip ETIs can be reused effectively to detect IRFs at the board level.

关键词： Power demand Network topology Instruments Fault detection Network-on-chip Maintenance engineering Hardware

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design and Analysis of Low Power and High Speed FinFET based Hybrid Full Adder/Subtractor Circuit (FHAS) 6

Design and Analysis of Low Power and High Speed FinFET based...

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6th ieee International symposium on Smart electronic systems (ieee-iSES)

作者： Ramkumar, E. Gracin, D. Rajkamal, P. Bhuvana, B. P. Bhaaskaran, V. S. Kanchana VIT Chennai Sch Elect Engn Chennai Tamil Nadu India

ISBN: (纸本)9781665404785

In this paper, two novel hybrid adder designs, namely, MASA and FHAS-2 have been proposed. these designs are designed using multiplexor, XOR and XNOR gates and they can be operated as both adder and subtractor modules effectively. A hybrid logic design principle has been utilized to construct the circuit structures. Transmission gate structures have been employed to realize the multiplexor design which determines whether addition or subtraction operation has to be performed by circuit. these circuits are designed using BSIMCMG FinFET 32nm technology files and the simulation is carried out using Cadence (R) Virtuoso tool. It is demonstrated that the proposed circuits incur lower power consumption and reduced delay compared to existing adder and subtractor circuit counterparts. Proposed circuits have been analyzed in terms of varying load and changing supply voltage conditions and the efficiency of FHAS-1 and FHAS-2 have been validated. It is observed that proposed FHAS-1 circuit is 81.25%, 42.13%, 25% and 13% more power efficient than the hybrid full adder circuit counterparts such as HFA -19T, HFA -22T, HFA -26T and HFA -17T, respectively.

关键词： Adder/Subtractor Low Power Adder Low Power Subtractor Hybrid arithmetic logic FinFET Adder

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International symposium on design and diagnostics of electronic circuits and systems

International Symposium on Design and Diagnostics of Electro...

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ieee International Test Conference (ITC)

作者： Stamenkovic, Zoran Bosio, Alberto Cserey, Gyorgy Novak, Ondrej Pleskacz, Witold Sekanina, Lukas Steininger, Andreas Stojanovic, Goran Stopjakova, Viera IHP Leibniz Inst Innovat Mikroelekt Frankfurt Oder Germany Ecole Cent Lyon Inst Nanotechnol Lyon Ecully France Pazmany Peter Catholic Univ Fac Informat Technol & Bion Budapest Hungary Tech Univ Liberec Fac Mechatron & Interdis Studies Liberec Czech Republic Warsaw Univ Technol Inst Microelect & Optoelect Warsaw Poland Brno Univ Technol Fac Informat Technol Brno Czech Republic Vienna Univ Technol Inst Comp Engn Vienna Austria Univ Novi Sad Fac Tech Sci Novi Sad Serbia Slovak Univ Technol Bratislava Fac Elect Engn & Informat Techn Bratislava Slovakia

ISBN: (纸本)9781728148236

the paper is a contribution to the 50th anniversary celebration of the International Test Conference (ITC) and its Global Test Forum (GTF), which honors the geographic breadth of the test community and highlights the global reach of ITC during the past 50 years. It covers the past, present, and future of the International symposium on design and diagnostics of electronic circuits and systems (DDECS), a symposium which belongs to prominent test technology related events initiated and supported by the ITC.

关键词： symposium DDECS electronics circuits systems

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A 10.5µW programmable SAR ADC Frontend with SC Preamplifier for Low-Power IoT Sensor Nodes 6

A 10.5µW programmable SAR ADC Frontend with SC Preamplifier...

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6th ieee World Forum on Internet of things, WF-IoT 2020

作者： Jotschke, Marcel Carvajal Ossa, Wilmar Reich, Torsten Mayr, Christian Fraunhofer IIS/EAS Fraunhofer Institute for Integrated Circuits Division Engineering of Adaptive Systems Dresden Germany Technische Universitaet Dresden Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits Dresden Germany

ISBN: (数字)9781728155036

ISBN: (纸本)9781728155036

Massive deployment of wireless autonomous sensor nodes requires their lifetime extension and cost reduction. the analog frontend (AFE) plays a key role in this context. this paper presents a successive approximation register analog-to-digital converter (SAR ADC) with a switched-capacitor programmable gain switched preamplifier (SCPGSA), as a basic component of an integrated ultra-low power AFE. AFE resolution, sample rate and signal gain are configurable between 6 to 13bit, 1 to 10kS/s and -6 to 12dB, respectively. the circuit draws 10.5µW from a 1.8V standard supply voltage, achieving an effective number of bits of 12.6bit and a Walden figure of merit of 169.1fJ/st. and 30.6fJ/st., computed with and without preamplifier, respectively. the circuit is employed in a modular internet of things sensor node, suitable to be solely powered from microenergy sources (energy harvesters). In order to feed charge-scaling SAR ADC inputs with the sensor voltages, typically a preamplifier stage is implemented, which can create energy overhead of magnitudes larger than the ADC power. this paper presents a duty-cycled preamplifier with programmable gain for SAR ADCs, utilizing switched-capacitor switched-opamp technique in the SCPGSA. No additional buffer circuitry is needed to charge the SAR ADC, and the preamplifier design is relaxed in power constraint. the circuit targets the low-cost internet of things market. Cost efficiency is achieved by technology choice, wide configurability and shortened ASIC design cycles. the latter results from partly generated layout, easing reuse of circuit parts from a different CMOS node. A testchip in a low-cost 180nm silicon-on-insulator technology was fabricated. © 2020 ieee.

关键词： Sensor nodes

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A tunable bandwidth 6th-order active low-pass filter in 0.18 um CMOS technology

A tunable bandwidth 6th-order active low-pass filter in 0.18...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Kristina Nikolić Jelena Radić Department of Power Electronic and Telecommunication Engineering University of Novi Sad Novi Sad Serbia

ISBN: (数字)9781728199382

ISBN: (纸本)9781728199399

In this paper, a tunable bandwidth 6 th -order active Butterworth low-pass filter has been designed in 0.18 um UMC CMOS technology. the topology consists of three second- order filters designed by using the Sallen-Key topology. the standard two-stage operation amplifier with Miller compensation capacitor is utilized as an operation amplifier stage in 2nd-order Butterworth low-pass filter. the cutoff frequency (3dB bandwidth) can be adjusted from 22 kHz to 52 kHz with a step value of 10 kHz by using a programmable capacitor bank. the post-layout simulation results show that for each cutoff frequency value, the designed tunable low-pass filter has a maximum passband attenuation of 11.53 mdB and a minimum stopband attenuation of 50 dB. the power consumption of designed active filter is 2.24 mW for a 1.8 V power supply. It achieves an in-band integrated input-referred noise of 130.502 uVrms and occupies active area of 0.65 mm 2 .

关键词： TV

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Random Forest Classifier for Hardware Trojan Detection 12

Random Forest Classifier for Hardware Trojan Detection

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12th International symposium on Computational Intelligence and design, ISCID 2019

作者： Xiang, Yiyao Li, Lei Zhou, Wanting University of Electronic Science and Technology of China Chengdu China

ISBN: (纸本)9781728146522

Hardware Trojans, which exist in the integrated circuits in the form of additional logic units, will affect the supply voltage of nearby units. In this paper, the ring oscillator is introduced to diagnose the state of the chip for its high sensitivity to the fluctuation of supply voltage. Combining the ring oscillator network, and the machine learning method, a random forest classifier is presented to detect hardware Trojans. the corresponding chips were designed and fabricated. the sample data, obtained from chips, were used to train the random forest classifier. the data can be processed by principal component analysis to optimize the random forest classifier. then the accuracy of the random forest classifier is improved. the experimental results show that the accuracy of this method is 100% for the UART-T100 chip with a Trojans ratio of 3.22% and the UART-T800 chip with a Trojan ratio of 1.67%. © 2019 ieee.

关键词： Principal component analysis

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Proceedings - 2015 ieee 18th International symposium on design and diagnostics of electronic circuits and systems, DDECS 2015

Proceedings - 2015 IEEE 18th International Symposium on Desi...

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18th ieee International symposium on design and diagnostics of electronic circuits and systems, DDECS 2015

ISBN: (纸本)9781479967803

the proceedings contain 59 papers. the topics discussed include: TPG for crosstalk faults between on-chip aggressor and victim using genetic algorithms;LFSR reseeding based test compression respecting different controllability of decompressor outputs;compiler-centred microprocessor design (CoMet) - from C-code to a VHDL model of an ASIP;a design for the 178-MHz WXGA 30-fps optical flow processor based on the HOE algorithm;design-for-diagnosis architecture for power switches;a novel compact dual-band bandpass waveguide filter;fully differential difference amplifier for low-noise applications;SystemC-based loose models for simulation speed-up by abstraction of RTL IP cores;NoCDepend: a flexible and scalable dependability technique for 3D networks-on-chip;a synchronous mirror delay with duty-cycle tunable technology;triangular modulation using switched-capacitor scheme for spread-spectrum clocking;and application of evolutionary algorithms for regression suites optimization.

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International symposium on design and diagnostics of electronic circuits and systems

International Symposium on Design and Diagnostics of Electro...

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ieee International Test Conference

作者： Zoran Stamenkovic Alberto Bosio Gyorgy Cserey Ondrej Novak Witold Pleskacz Lukas Sekanina Andreas Steininger Goran Stojanovic Viera Stopjakova IHP - Leibniz-Institut für innovative Mikroelektronik Frankfurt (Oder) Germany Institute of Nanotechnology of Lyon Ecole Centrale de Lyon Ecully France Faculty of Information Technology and Bionics Pazmany Peter Catholic University Budapest Hungary Faculty of Mechatronics and Interdis. Studies Technical University of Liberec Liberec Czechia Institute of Microelectr. and Optoelectronics Warsaw University of Technology Warsaw Poland Faculty of Information Technology Brno University of Technology Brno Czechia Institute of Computer Engineering Vienna University of Technology Vienna Austria Faculty of Technical Sciences University of Novi Sad Novi Sad Serbia Faculty of Elect. Eng. and Information Techn. Slovak University of Technology Bratislava Slovakia

ISBN: (数字)9781728148236

ISBN: (纸本)9781728148243

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