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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是121-130 订阅

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Automated Phase-Noise-Aware design of RF Clock Distribution circuits

Automated Phase-Noise-Aware Design of RF Clock Distribution ...

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作者： Martev, Dimo Hampel, Sven Schlichtmann, Ulf Department of Electronic Design Automation Technical University of Munich Munich80333 Germany Sennheiser Electronic GmbHandCo KG Wedemark30900 Germany

this paper presents a methodology for phase-noise-aware design of RF clock distribution networks. the methodology is embedded within a commercial digital toolchain. It consists of a method for phase noise analysis based on lookup tables, a buffer insertion algorithm providing an optimal buffering for large interconnect trees and a gate sizing algorithm that offers fast power minimization, subject to noise constraints. the phase noise estimate produced by the proposed method on average deviates by less than 3.45% from SPICE simulation results;however, it can be computed three to five orders of magnitude faster. the proposed buffer insertion methodology can easily handle very large industrial examples. It completes within seconds, compared to days for methodologies used in industry today. the gate sizing optimization offers three to four orders of magnitude speedup, compared to commercial products, while producing comparable results. the proposed design methodology reduces the design time of RF clock distribution networks from weeks to a few hours by eliminating the need for manual circuit design, analog simulations, and manual layout. To the extent of our knowledge, this is the first paper on the design automation of RF clock distribution networks. © 2018 ieee.

关键词： Phase noise

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Logic Testing with Test-per-Clock Pattern Loading and Improved Diagnostic Abilities 20

Logic Testing with Test-per-Clock Pattern Loading and Improv...

引用

20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Novak, Ondrej Pliva, Zdenek Tech Univ Liberec Studentska 2 Liberec 46117 I Czech Republic

ISBN: (纸本)9781538604724

this paper describes a test response compaction system that preserves diagnostic information and enables performing a test-per-c1ock offline testing. the test response compaction system is based on a chain of T flip-flops. the T flip-flop signature chain can preserve the information about the position of the first occurrence of the erroneous test response and the information about the clock cycle when the erroneous test response occurred. this information can be used for diagnostic purposes. the paper discusses the possible benefits and limitations of the proposed test pattern compaction scheme. the influence of multiple errors on detection and localization capability of the compaction system and hardware overhead is discussed in the paper as well.

关键词： design for testability (DFT) scan-based test linear finite state machines

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Implementation of an Asynchronous Bundled-Data Router for a GALS NoC in the Context of a VSoC 20

Implementation of an Asynchronous Bundled-Data Router for a ...

引用

20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Russell, Patrick Doege, Jens Hoppe, Christoph Preusser, thomas B. Reichel, Peter Schneider, Peter Fraunhofer Inst Integrated Circuits HS Div Engn Adapt Syst EAS Erlangen Germany Tech Univ Dresden Inst Comp Engn Dresden Germany

ISBN: (纸本)9781538604724

designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implementation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. this paper proposes the design and implementation of an asynchronous router architecture suitable for a network-on-chip in the context of a Vision-System-on-Chip. the developed design flow for the synthesis of asynchronous bundled-data pipelines is based on common synthesis tools and, therefore, enables high compatibility with synchronous designs and a low barrier to entry.

关键词： network-on-chip low power low latency GALS asynchronous circuits vision-system-on-chip CAD synthesis

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Analog Front-End for Precise Human Body Temperature Measurement 20

Analog Front-End for Precise Human Body Temperature Measurem...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Narczyk, Pawel Siwiec, Krzysztof Pleskacz, Witold A. Warsaw Univ Technol Inst Microelect & Optoelect Ul Koszykowa 75 PL-00662 Warsaw Poland

ISBN: (纸本)9781538604724

Analog front-end for precise temperature measurement of a human body has been presented. the discussed analog front-end (AFE) contains a new temperature calibration technique based on on-chip resistor. the described calibration method allows to obtain very high accuracy, even 0.1 DC, in very wide range of an operating temperature of an integrated circuit. the AFE consists of a bandgap current reference, a precision current source, a programmable gain amplifier, a voltage source proportional to absolute temp erature and on-chip temperature calibration resistor. the presented analog front-end consumes no more than 180 uW and was designed and manufactured in UMC CMOS 130 nm technology. All data presented in the article were obtained from measurements. Measurements were taken using manual wafer prober with climate control microchamber, at temperature range from -40 degrees C to 125 degrees C.

关键词： biomedical circuits and systems human body temperature measurement skin temperature analog front-end (AFE) current reference current source programmable gain amplifier proportional to absolute temperature voltage source (PTAT) CMOS 130 nm, measurements, measurements results

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An Efficient Physical design of Fully-testable BDD-based circuits 20

An Efficient Physical Design of Fully-testable BDD-based Cir...

引用

20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Rauchenecker, Andreas Wille, Robert Johannes Kepler Univ Linz Inst Integrated Circuits Linz Austria

ISBN: (纸本)9781538604724

For the manufacturing test of ASICs, it is important to reach a high test coverage in order to get the defect level as low as possible. However, complex digital circuits are usually not fully testable. In order to address that, previous work suggested to realize the circuits by means of Binary Decisions Diagrams (BDDs). Here, each node is implemented using multiplexer gates (MUX gates) which, with some minor additions, yield 100% testable circuits with respect to stuck-at and path-delay faults. Unfortunately, current physical implementations of MUX gates are rather expensive with respect to propagation delay, power consumption, or transistor count. Hence, despite the prospect of gaining 100% testability, BDD-based circuits did not find significant attention yet. In this work, we propose an alternative realization of MUX gates based on pass transistor logic which addresses these drawbacks. Experiments show that this allows for the realization of fully testable BDD-based circuits which are competitive to or, in many cases, even better than state-of- the-art realizations.

关键词： Logic gates Transistors Circuit faults Physical design Boolean functions Multiplexing Standards

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Body Biasing for Analog design: Practical Experiences in 22 nm FD-SOI 20

Body Biasing for Analog Design: Practical Experiences in 22 ...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Rao, Sunil Satish Prautsch, Benjamin Shrivastava, Ashish Reich, Torsten Fraunhofer IIS EAS Inst Integrated Circuits Div Engn Adapt Syst Dresden Germany

ISBN: (纸本)9781538604724

this paper presents the practical application of body biasing control of ultra-deep submicron FD-SOI technologies for analog and mixed-signal designs. the body biasing control is dedicated for dynamic control of the trade-off between speed vs. power consumption for advanced digital circuits. However, in this work we focus on trading-off and improvement of analog circuit performances. three different circuits were explored and designed: an all CMOS bandgap reference, a 500 MSps current-steering DAC, and a 12-bit sigma-delta modulator. All designs were verified and realized in Globalfoundries 22 nm FD-SOI technology.

关键词： Ultra deep submicron 22 nm FD-SOI Data converters Reference generators Body biasing Analog design

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Structure-Preserving Modeling of Safety-Critical Combinational circuits 20

Structure-Preserving Modeling of Safety-Critical Combination...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Rasim, Feim Ridvan Kocar, Canan Sattler, Sebastian M. Friedrich Alexander Univ Erlangen Nuremberg Chair Reliable Circuits & Syst Paul Gordan Str 5 D-91052 Erlangen Germany

ISBN: (纸本)9781538604724

In this work, a representative combinational circuit is abstracted from transistor level to gate level and a structure preserving transition is carried out into a signal flow graph. For creating a signal flow plan it is necessary to swap the nodes and the edges in the signal flow graph. After executing this action the result is a signal flow plan. A value table exhibits the coding of the whole circuit. then the so called module view is used to get the familiar compact display and neighborhood relations are repeated once more, the resolution method is used. It is observed that in digital circuits, undefined results can occur but these must be avoided in safety critical circuits. these events have to be secured in practice by costly and expensive verification and testing. In order to deal with the problem now, the structure preserving modeling has to be understood, since this is the only way to achieve a one-purpose, qualitative and cost effective search for errors.

关键词： Combinational circuit structure modeling symbolic analysis signal flow graph Boolean function

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A Scalable Technique to Identify True Critical Paths in Sequential circuits 20

A Scalable Technique to Identify True Critical Paths in Sequ...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ubar, Raimund Kostin, Sergei Jenihhin, Maksim Raik, Jaan Tallinn Univ Technol Tallinn Estonia

ISBN: (纸本)9781538604724

the recent advancements in the implementation technologies have brought to the front a wide spectrum of new defect types and reliability phenomena. the conventional design techniques do not cope with the integration capacity and stringent requirements of today's nanometer technology nodes. Timing-critical paths analysis is one of such tasks. It has applications in gate-level reliability analysis, e.g., Bias Temperature Instability (BTl) induced aging, but also several others. In this paper, we propose a scalable simulation based technique for explicit identification of true timing-critical paths in both combinational and sequential circuits to enable reliability mitigation approaches, like deciding the paths for delay monitor insertion, resizing delay critical gates or applying rejuvenation stimuli. the paper demonstrates an efficient application of the proposed technique to gate-level NBTI-critical paths identification. the experimental results prove feasibility and scalability of the technique.

关键词： timing-critical path gate-level analysis NETI

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Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches 20

Optimization of Pearson correlation coefficient calculation ...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Socha, Petr Miskovsky, Vojtech Kubatova, Hana Novotny, Martin Czech Tech Univ Fac Informat TechnOl Dept Digital Design Prague Czech Republic

ISBN: (纸本)9781538604724

Differential power analysis (DPA) is one of the most common side channel attacks. To perform this attack we need to calculate a large amount of correlation coefficients. this amount is even higher when attacking FPGAs or ASICs, for higher order attacks and especially for attacking DPA protected devices. this article explains different approaches to the calculation of correlations, describes our implementation of these approaches and presents a detailed comparison considering their performance and their properties for a practical usage.

关键词： Differential Power Analysis DPA Pearson correlation coefficient AES Side Channel Attack

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Fault Detection and Self Repair in Hsiao-Code FEC circuits 20

Fault Detection and Self Repair in Hsiao-Code FEC Circuits

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Dicorato, Davide Pfeifer, Petr Vierhaus, Heinrich T. BTU Cottbus Senftenberg Comp Engn Grp Senftenberg Germany

ISBN: (纸本)9781538604724

Wireless signal transmission has become the essential core of modern comm unication systems. Forward error correction (FEC) has a critical role in securing quality and reliability. FEC circuitry, implemented in nano-technologies, may suffer from transient and permanent fault effects such as radiation-induced single event upsets (SEUs) and aging effects. Such circuits may actually mask non-permanent hardware faults, but possibly at the expense of transmission error correction. Single error correction (SEC) double error detection (DED) methods are favorably used for rapid error correction within a single clock cycle, and they may even be used for multiple error correction in iterative approaches. But such schemes fail in case hardware faults and transmission faults combine. Where FEC circuits are used in systems that need to be highly dependable over a long life time or which may have limited access for repair, the option of built-in self repair (BISR) may become a must.

关键词： error correction self test self repair

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