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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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design for three-Dimensional Sound Processor using High-Level Synthesis 20

Design for Three-Dimensional Sound Processor using High-Leve...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ohira, Saya Matsumura, Tesuya Nihon Univ Grad Sch Engn & Technol Koriyama Fukushima Japan Nihon Univ Coll Engn Koriyama Fukushima Japan

ISBN: (纸本)9781538604724

We propose a three-dimensional (3D) sound processor architecture that includes super-directional modulation intellectual property (IP) and 3D sound processing IP for consumer applications. this processor can generate realistic small sound fields in arbitrary spaces by using ultrasound. the architecture is designed with high-level synthesis as the design methodology. By inputting a description of several design parameters, such as the number of IPs and the order and coefficients of the filters on SystemC, the pro cesser hardware can be synthesized automatically. the total amount of hardware used for the super-directional modulation IP and the 3D sound processing IP is 6,02 1 Nets and 1,292 LCs. the 3D sound processor was implemented on a Xilinx FPGA to verify its function and performance.

关键词： sound processer super-directional sound ultra sound high-level synthesis FPGA

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Formal design Space Exploration for Memristor-based Crossbar Architecture 20

Formal Design Space Exploration for Memristor-based Crossbar...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Traiola, Marcello Barbareschi, Mario Bosio, Alberto Univ Montpellier CNRS LIRMM Montpellier France Univ Naples Federico II DIETI Naples Italy

ISBN: (纸本)9781538604724

the unceasing shrinking process of CMOS technology is leading to its physical limits, impacting several aspects, such as performances, power consumption and many others. Alternative solutions are under investigation in order to overcome CMOS limitations. Among them, the memristor is one of promising technologies. Several works have been proposed so far, describing how to synthesize boolean logic functions on memristors-based crossbar architecture. However, depending on the synthesis parameters, different architectures can be obtained. design Space Exploration (DSE) is therefore mandatory to help and guide the designer in order to select the best crossbar configuration. In this paper, we present a formal DSE approach. the main advantage is that it does not require any simulation and thus it avoids any runtime overheads. Preliminary results show the huge gain in runtime compared to simulation-based DSE.

关键词： Memristor crossbar design Space Exploration Boolean Functions Circuit Synthesis

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Routing Approach for Digital, Differential Bipolar designs using Virtual Fat-Wire Boundary Pins 20

Routing Approach for Digital, Differential Bipolar Designs u...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Schrape, Oliver Herrmann, Manuel Winkler, Frank Krstic, Milos IHP Technol Pk 25 D-15236 Frankfurt Oder Germany Humboldt Univ Unter Linden 6 D-10099 Berlin Germany

ISBN: (纸本)9781538604724

this paper presents an alternative fat-wire routing approach for differential bipolar high-speed designs. the proposed solution obtains parallel routing and well balanced capacitive load of the fully differential signaling. In contrast to other approaches, the proposed flow is optimized for complex bipolar CML/ECL standard cell designs and technology options with few available routing layers. It enables the use of advanced placement and routing methods, such as multi-oriented cell placement and in-place optimization, supported by the standard CAD tools. the standard cell requirements and the corresponding modified digital design flow are proposed and discussed. the presented strategy is evaluated on a 12.5 GHz PLL feedback clock divider which has been fully implemented with differential ECL standard cell gates. A discussion regarding the obtained results finalizes this paper.

关键词： Fat-wire Routing Differential Signaling ECL CML Current Mode Logic Digital design design Flow

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HLS design of a Hardware Accelerator for Homomorphic Encryption 20

HLS Design of a Hardware Accelerator for Homomorphic Encrypt...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Mkhinini, A. Maistri, P. Leveugle, R. Tourki, R. Univ Grenoble Alpes CNRS Grenoble INP Inst EngnTIMA F-38000 Grenoble France Univ Monastir E E Monastir 5019 Tunisia Univ Sousse Eniso BP 264 Erriadh 4023 Tunisia

ISBN: (纸本)9781538604724

Modular polynomial multiplication is the most computationally intensive operation in many homomorphic encryption schemes. In order to accelerate homomorphic computations, we propose a software/hardware (SW/HW) co-designed accelerator integrating fast software algorithms with a configurable hardware polynomial multiplier. the hardware accelerator is implemented through a High-Level Synthesis (HLS) flow. We show that our approach is highly flexible, since the same generic high-level description can be configured and reused to generate a new design with different parameters and very large sizes in negligible time. We show that flexibility does not preclude efficiency : the proposed solution is competitive in comparison with hand-made designs and can provide good performance at low cost.

关键词： Homomorphic encryption modular polynomial multiplication High Level Synthesis

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Novel Metrics for Analog Mixed-Signal Coverage 20

Novel Metrics for Analog Mixed-Signal Coverage

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Fuertig, Andreas Glaeser, Georg Grimm, Christoph Hedrich, Lars Heinen, Stefan Lee, Hyun-Sek Lukas Nitsche, Gregor Olbrich, Markus Radojicic, Carna Speicher, Fabian Goethe Univ Frankfurt Inst Comp Sci Frankfurt Germany IMMS Inst Mikroelekt & Mechatron Syst Gemeinnutzi Ilmenau Germany Kaiserslautern Univ Technol Design Cyber Phys Syst Kaiserslautern Germany Leibniz Univ Hannover Inst Microelect Syst Hannover Germany Inst Informat Technol OFFIS Oldenburg Germany Rhein Westfal TH Aachen Chair Integrated Analog Circuits Aachen Germany

ISBN: (纸本)9781538604724

On the contrary to the digital world, no coverage definition exists in the Analog/Mixed-Signal (AMS) context. As digital coverage helps digital designers and verification engineers to evaluate their verification progress, analog designers do not have such metrics. this paper proposes a set of different analog coverage metrics, which improve the confidence in AMS circuit verification. We will demonstrate, that no single overall coverage metric exists. However, as with digital coverage, the proposed analog coverage metrics could substantially help in rating the verification process. Illustrated by a complex AMS circuit example we will explore the limits of analog coverage methodologies as well as the benefits on different levels of abstraction ranging from transistor level up to system level.

关键词： Analog circuits Integrated circuit modeling Transient analysis Phase locked loops Computational modeling Transmission line measurements

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design-for-FAST: Supporting X-tolerant Compaction during Faster-than-at-Speed Test 20

Design-for-FAST: Supporting X-tolerant Compaction during Fas...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kampmann, Matthias Hellebrand, Sybille Paderborn Univ Warburger Str 100 D-33098 Paderborn Germany

ISBN: (纸本)9781538604724

Small Delay Faults (SDFs) on short paths may escape even state-of-the-art at-speed tests. Faster-than-at-Speed Test (FAST) works with increased clock frequencies to detect these faults. However, FAST also introduces an increased amount of unknown logic values (X-values) into the test responses, which makes test response compaction difficult. the paper at hand presents and evaluates a design for Test (DFT) approach specifically tuned to FAST. It utilizes a special scan-chain configuration in combination with an adaptive masking scheme - the required mask data is generated by respective frequency-aware algorithms. Experimental results indicate that this combination of scan-chain configuration and output masking can achieve high reduction in X-values (up to 95 %) without too much loss of fault information at a reasonable amount of control overhead. the approach also has a significant impact on the number of intermediate signatures required by an X-canceling MISR, which can be reduced by up to 68 %.

关键词： FAST BIST DFT Scan chain configuration X-masking

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Mapping Abstract and Concrete Hardware Models for design Understanding 20

Mapping Abstract and Concrete Hardware Models for Design Und...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Flenker, Tina Fey, Goerschwin Univ Bremen Inst Comp Sci D-28359 Bremen Germany German Aerosp Ctr Inst Space Syst D-28359 Bremen Germany

ISBN: (纸本)9781538604724

Before a microchip's concrete implementation is available a very abstract model is created, e.g., on electronic System Level (ESL) or even more abstract. To ensure a better design understanding, we propose an automated mapping from a given abstract model to an unfamiliar concrete implementation at Register Transfer Level (RTL). But how to map a variable from the abstract model to a variable from the concrete model? We address this problem by a simulation based approach. We instrument the abstract model to get traces for each variable in both models and propose four heuristics to evaluate which variable maps to a corresponding variable of the other model. Experiments on an Instruction Set Simulator (ISS) versus RTL processor show mappings which offer an insight into the RTL implementation.

关键词： design Understanding

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PMS2UPF: An Automated Transition from ESL to RTL Power-Intent Specification 20

PMS2UPF: An Automated Transition from ESL to RTL Power-Inten...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Siro, Miroslav Macko, Dominik Jelemenska, Katarina Slovak Univ Technol Bratislava Fac Informat & Informat Technol Bratislava Slovakia

ISBN: (纸本)9781538604724

High power density is the most crucial problem in deeply integrated hardware systems. therefore, the power has to be reduced in such systems, what is most commonly achieved by the utilization of power management. Unfortunately, the standardized application of power management is quite complex and does not very well support the system level of design abstraction, which is increasingly used by the industry. An immediately applicable solution to this problem is to use increased automation in the design process, regarding the power management. this paper proposes a tool, called PMS2UPF, which can automatically generate the standard UPF (Unified Power Format) power intent based on the abstract power-management specification in SystemC/PMS. the automated transition between the two abstraction levels not only accelerates the design process, but also prevents possible introduction of human errors into the refined design.

关键词： design automation electronic system level high level synthesis low power electronics power control

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A 50 GHz SiGe BiCMOS Active Bandpass Filter 20

A 50 GHz SiGe BiCMOS Active Bandpass Filter

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Chaturvedi, Saurabh Bozanic, Mladen Sinha, Saurabh Univ Johannesburg Dept Elect & Elect Engn Sci Fac Engn & Built Environm Auckland Pk Kingsway Campus Johannesburg South Africa

ISBN: (纸本)9781538604724

this paper presents a second-order active bandpass filter (BPF) at millimeter-wave frequency band using 0.13 mu m SiGe BiCMOS technology. A complementary cross-coupled pair based negative resistance technique is applied to compensate for the resistive losses of microstrip line resonators. the proposed active BPF is simulated using the Keysight Technologies (formerly Agilent' s electronic Measurement Group) Advanced design System 2016.01. the center frequency (f(c)), 3-dB bandwidth, and fractional bandwidth of the simulated BPF are 53.85 GHz, 14.18 GHz, and 26.33 %, respectively. the BPF shows an insertion loss (IL) of 0.33 dB and a return loss (RL) of 18.03 dB f(c). the minimum IL of 0.10 dB and best RL of 26.03 dB are observed in the passband. the noise figure and input 1-dB compression point (PldB) f(c) are 7.93 dB and -3.67 dBm, respectively. the power dissipation is 2.62 mW at 1.6 V supply voltage. For the input power level of -10 dBm, the power level of the second harmonic is -46.02 dBc.

关键词： Bandpass filter (BPF) SiGe BiCMOS negative resistance loss compensation resonator process design kit (PDK)

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Relaxed equivalence checking: a new challenge in logic synthesis 20

Relaxed equivalence checking: a new challenge in logic synth...

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20th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Vasicek, Zdenek Brno Univ Technol Fac Informat Technol Ctr Excellence IT4Innovat Bozetechova 2 Brno 61266 Czech Republic

ISBN: (纸本)9781538604724

the functional equivalence has always been the integral part of virtually every logic synthesis tool. the formal equivalence checking represents a key process that helps logic synthesis tool guarantee that two representations of a circuit design exhibit exactly the same behavior, Among others, equivalence checking is routinely applied to prove that a synthesized digital circuit is logically equivalent to the RTL source code, Although formal equivalence checking has matured greatly during the last two decades and designs with millions of gates can be handled and verified in reasonable time, a new challenge has emerged with the recent advent of approaches addressing the problem of synthesis of approximate circuits, Approximate circuits are digital circuits which are intentionally designed in such a way that the specification is violated in terms of functionality in order to obtain some improvements in power consumption, performance or area, in comparison with fully functional circuits. the main problem related to the synthesis of approximate circuits is the checking that the synthesized circuits meet the specification. the nature of the approximate circuits involves to replace the strict formal equivalence checking with more advanced methods that enable to perform so called relaxed equivalence checking, i.e. checking that two circuit designs are equal up to some bound. In addition to that, it is crucial to perform the checking as quickly as possible because this procedure is employed in iterative design process. Compared to the formal equivalence checking, only little has been done in this area and the relaxed equivalence checking still represents an open and challenging problem. the purpose of this paper is to survey and briefly introduce the methods proposed to address the problem of relaxed equivalence checking especially in the context of approximate computing and summarize and discuss the main challenges of this research problem in the context of logic synthesis.

关键词： Measurement Tools Approximate computing design methodology Error analysis Artificial neural networks Power demand

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