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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC

Implementation of an asynchronous bundled-data router for a ...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Patrick Russell Jens Döge Christoph Hoppe thomas B. Preußer Peter Reichel Peter Schneider Divison Engineering of Adaptive Systems EAS Fraunhofer Institute for Integrated Circuits IIS Technische Universitat Dresden Dresden Sachsen DE

designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implementation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. this paper proposes the design and implementation of an asynchronous router architecture suitable for a network-on-chip in the context of a Vision-System-on-Chip. the developed design flow for the synthesis of asynchronous bundled-data pipelines is based on common synthesis tools and, therefore, enables high compatibility with synchronous designs and a low barrier to entry.

关键词： Delays Tools Pipelines Routing Asynchronous circuits Routing protocols

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Ultra-low-voltage driver for large load capacitance in 130nm CMOS technology

Ultra-low-voltage driver for large load capacitance in 130nm...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Michal Šovčík Martin Kováč Daniel Arbet Viera Stopjaková Department of IC Design and Test Slovak University of Technology Bratislava Slovakia

this paper presents design of the inverter-based driver for low-voltage applications, with topology for boosting the transistors overdrive voltage. the proposed driver topology was designed through detailed circuit analysis and optimization, and it is suitable for use in a switched capacitor charge pump. the driver was designed in 130 nm CMOS technology and verified by simulations including technology corners. Core of the proposed driver - the inverter uses power supply voltage of 200 mV. the whole boosted driver achieves a propagation delay of 9.2 ns and energy consumption of 92.12 μW for the value of load capacitor is 100 pF. Due to the low-power consumption, the proposed driver was satisfactory used in a self-powered charge pump systems.

关键词： Capacitors Inverters Topology MOSFET Capacitance Charge pumps

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Mapping abstract and concrete hardware models for design understanding

Mapping abstract and concrete hardware models for design und...

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Tino Flenker Görschwin Fey University of Bremen Institute of Computer Science Bremen Germany Institute of Space Systems German Aerospace Center Bremen Germany

Before a microchip's concrete implementation is available a very abstract model is created, e.g., on electronic System Level (ESL) or even more abstract. To ensure a better design understanding, we propose an automated mapping from a given abstract model to an unfamiliar concrete implementation at Register Transfer Level (RTL). But how to map a variable from the abstract model to a variable from the concrete model? We address this problem by a simulation based approach. We instrument the abstract model to get traces for each variable in both models and propose four heuristics to evaluate which variable maps to a corresponding variable of the other model. Experiments on an Instruction Set Simulator (ISS) versus RTL processor show mappings which offer an insight into the RTL implementation.

关键词： Concrete Computational modeling Timing Analytical models Hardware Hardware design languages Pipeline processing

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A 50 GHz SiGe BiCMOS active bandpass filter

A 50 GHz SiGe BiCMOS active bandpass filter

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Saurabh Chaturvedi Mladen Božanić Saurabh Sinha Department of Electrical and Electronic Engineering Science University of Johannesburg Johannesburg South Africa

this paper presents a second-order active bandpass filter (BPF) at millimeter-wave frequency band using 0.13 μm SiGe BiCMOS technology. A complementary cross-coupled pair based negative resistance technique is applied to compensate for the resistive losses of microstrip line resonators. the proposed active BPF is simulated using the Keysight Technologies (formerly Agilent's electronic Measurement Group) Advanced design System 2016.01. the center frequency (f c ), 3-dB bandwidth, and fractional bandwidth of the simulated BPF are 53.85 GHz, 14.18 GHz, and 26.33%, respectively. the BPF shows an insertion loss (IL) of 0.33 dB and a return loss (RL) of 18.03 dB at f c . the minimum IL of 0.10 dB and best RL of 26.03 dB are observed in the passband. the noise figure and input 1-dB compression point (P 1dB ) at f c are 7.93 dB and -3.67 dBm, respectively. the power dissipation is 2.62 mW at 1.6 V supply voltage. For the input power level of -10 dBm, the power level of the second harmonic is -46.02 dBc.

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Impedance calculation based method for AC fault analysis of mixed-signal circuits 19

Impedance calculation based method for AC fault analysis of ...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Brenkus, Juraj Stopjakava, Viera Nagy, Lukas Arbet, Daniel Slovak Univ Technol Bratislava Dept Integrated Circuits Design & Test Bratislava Slovakia

ISBN: (纸本)9781509024674

An alternative method of fault simulation is presented in this paper. the proposed method is based on impedance calculations in the circuit under test. Calculation time and other properties of the method are addressed and evaluated. Possible application and results evaluation are demonstrated on an experimental circuit. this method could improve the test development time and quality.

关键词： Timing circuits

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Novel metrics for Analog Mixed-Signal coverage

Novel metrics for Analog Mixed-Signal coverage

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Andreas Fürtig Georg Gläser Christoph Grimm Lars Hedrich Stefan Heinen Hyun-Sek Lukas Lee Gregor Nitsche Markus Olbrich Carna Radojicic Fabian Speicher Institute for Computer Science Goethe Universität Frankfurt a. M. Germany IMMS Institut für Mikroelektronik-und Mechatronik-Systeme gemeinnützige GmbH Ilmenau Germany Design of Cyber-Physical Systems Kaiserslautern University of Technology Germany Chair of Integrated Analog Circuits RWTH Aachen University Germany Institute of Microelectronic Systems Leibniz Universität Hannover Germany OFFIS Institute for Information Technology Germany

On the contrary to the digital world, no coverage definition exists in the Analog/Mixed-Signal (AMS) context. As digital coverage helps digital designers and verification engineers to evaluate their verification progress, analog designers do not have such metrics. this paper proposes a set of different analog coverage metrics, which improve the confidence in AMS circuit verification. We will demonstrate, that no single overall coverage metric exists. However, as with digital coverage, the proposed analog coverage metrics could substantially help in rating the verification process. Illustrated by a complex AMS circuit example we will explore the limits of analog coverage methodologies as well as the benefits on different levels of abstraction ranging from transistor level up to system level.

关键词： Analog circuits Integrated circuit modeling Transient analysis Phase locked loops Computational modeling Transmission line measurements

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8 Channel Neural Stimulation ASIC for Epidural Visual Cortex Stimulation with on Board 90 ppm/°C Current Reference 19

8 Channel Neural Stimulation ASIC for Epidural Visual Cortex...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Osipov, Dmitry Paul, Steffen Univ Bremen Inst Electrodynam & Microelect ITEM Otto Hahn Allee 1 D-28359 Bremen Germany

ISBN: (纸本)9781509024674

this paper presents an 8 channel neural stimulator ASIC for biphasic stimulation of the visual cortex, realized in a 0.35 mu m AMS HV process. Each channel is composed of an SPI interface, an 8-bit current digital-to-analog converter (DAC) and 120 V compliant HV output stage. thus it is possible to deliver to the tissue arbitrary current waveforms with amplitudes up to +/- 10.24 mA with 40 mu A steps. According to the simulation results the maximum differential non-linearity is equal to 0.27 LSB. the on board current reference provides the output current of 16 mu A with the variation of 90 ppm/degrees C in the temperature range of 0-85 degrees C. While the anodic and cathodic currents mismatch does not exceed 13 mu A. the HV output interface of the ASIC was previously fabricated and measured. the measured interpulse leakage current does not exceed 60 pA.

关键词： Application specific integrated circuits

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Implementation of a Real Time Unit for Satellite Applications 19

Implementation of a Real Time Unit for Satellite Application...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Simevski, Aleksandar Schleisiek, Klaus Petrovic, Vladimir Beller, Norbert Skoncej, Patryk Schoof, Gunter Krstic, Milos IHP Technol Pk 25 D-15236 Frankfurt Oder Germany SpaceTech Seelbachstr 13 D-88090 Immenstaad Germany

ISBN: (纸本)9781509024674

the significance of low cost small satellites used for scientific research and practical applications continuously grows. Current satellite OBC (On-Board Computer) microcontrollers have integrated various digital peripherals and interfaces. However, a common Real Time Unit (RTU) requires interfacing to simple analogue sensors and actuators. Here we present a novel RTU microcontroller which includes a 13-bit Analog-to-Digital Converter (ADC) and two 12-bit Digital-to-Analog Converters (DAC). Furthermore, it includes a 32KB internal SRAM memory and a 32KB internal flash memory. this enables an easy construction of a software-controlled embedded system which is easily interfaced to existing hardware sensors and actuators. the chip is produced in IHP 250nm technology using radiation hardening by design. the operating frequency is 80 MHz. A 3-bit clock divider, as well as clock-and power-gating are used for reducing power consumption which is measured to be 0,8W in operation.

关键词： Microcontrollers

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Early-Stage Verification of Power-Management Specification in Low-Power systems design 19

Early-Stage Verification of Power-Management Specification i...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Macko, Dominik Jelemenska, Katarina Cicak, Pavel Slovak Univ Technol Bratislava Fac Informat & Informat Technol Bratislava Slovakia

ISBN: (纸本)9781509024674

Power consumption becomes a dominant problem in current hardware-systems design. It is most commonly dealt with use of power-management techniques, such as clock gating, power gating, or voltage and frequency scaling. In modern complex systems, power-management adoption is difficult to achieve, and therefore new approaches to simplify power-managed systems design are evolving. We have also proposed such an approach, simplifying power-management specification at the system level of design abstraction. this paper describes the proposed verification approach, which can take place continuously, beginning at the early specification stage of the system development. It helps a designer to create correct and consistent specification of power management.

关键词： hardware design low power power management specification verification

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the design Features of Low-Temperature Radiation-Hardened Instrumentation Amplifiers and Sensor Interfaces 19

The Design Features of Low-Temperature Radiation-Hardened In...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Titov, A. E. Prokopenko, N. N. Pakhomov, I. V. Southern Fed Univ Rostov Na Donu Russia Don State Tech Univ Rostov Na Donu Russia

ISBN: (纸本)9781509024674

the article gives a theoretical analysis of the generalized structure of precision instrumentation amplifiers (IA) of modern interfaces for sensor and diagnostic systems of robots and unmanned aerial vehicles (UAV), which operate, among others, on exposure to radiation and low temperatures. the main disadvantages of classical IA are determined from the common positions and the possible ways of their clearing are presented. the new architecture of radiation-hardened differential difference op-amp (DDA) based on "folded" cascode is developed for the application in sensor interfaces and its simulation results are given, taking into account the effect of disturbing factors.

关键词： robot sensor interface analog microcircuits instrumentation amplifier neutron flux low temperatures

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