检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

665 篇 会议
18 篇 期刊文献

馆藏范围

683 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

472 篇 工学
- 398 篇 电气工程
- 185 篇 电子科学与技术（可...
- 151 篇 计算机科学与技术...
- 24 篇 材料科学与工程（可...
- 16 篇 软件工程
- 8 篇 机械工程
- 7 篇 信息与通信工程
- 7 篇 控制科学与工程
- 4 篇 交通运输工程
- 3 篇 安全科学与工程
- 2 篇 动力工程及工程热...
- 2 篇 建筑学
- 2 篇 土木工程
- 2 篇 化学工程与技术
- 2 篇 网络空间安全
- 1 篇 力学（可授工学、理...
- 1 篇 仪器科学与技术
- 1 篇 林业工程
13 篇 理学
- 7 篇 数学
- 5 篇 物理学
- 3 篇 系统科学
- 1 篇 统计学（可授理学、...
6 篇 管理学
- 5 篇 管理科学与工程(可...
- 1 篇 图书情报与档案管...

主题

36 篇 hardware
31 篇 field programmab...
30 篇 circuit faults
29 篇 cmos integrated ...
22 篇 logic gates
21 篇 integrated circu...
21 篇 clocks
20 篇 digital circuits
19 篇 reliability
19 篇 circuit testing
19 篇 algorithm design...
19 篇 delay
19 篇 cmos technology
17 篇 power demand
17 篇 electronic circu...
16 篇 timing circuits
15 篇 analog circuits
15 篇 fpga
14 篇 hardware design ...
14 篇 optimization

机构

12 篇 faculty of infor...
8 篇 univ bremen inst...
8 篇 brno univ techno...
7 篇 slovak univ tech...
6 篇 ihp technol pk 2...
5 篇 institute of com...
5 篇 univ oslo dept i...
5 篇 warsaw univ tech...
4 篇 ihp im technolog...
4 篇 univ tokyo vlsi ...
4 篇 univ manchester ...
4 篇 dfki gmbh cyber ...
4 篇 brno univ techno...
4 篇 silesian tech un...
4 篇 infineon technol...
4 篇 st microelect gr...
4 篇 norwegian univer...
4 篇 warsaw univ tech...
4 篇 ihp
3 篇 johannes kepler ...

作者

12 篇 sekanina lukas
11 篇 stopjakova viera
11 篇 pleskacz witold ...
10 篇 drechsler rolf
10 篇 asada kunihiro
8 篇 rolf drechsler
8 篇 steininger andre...
8 篇 kerkhoff hans g.
7 篇 kubatova hana
7 篇 krstic milos
7 篇 raik jaan
7 篇 ubar raimund
7 篇 bosio alberto
7 篇 vierhaus heinric...
7 篇 borejko tomasz
6 篇 arbet daniel
6 篇 siwiec krzysztof
6 篇 viera stopjakova
6 篇 nakura toru
6 篇 klaus hofmann

语言

682 篇 英文
1 篇 中文

检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是161-170 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Comparing Proton and Neutron Induced SEU Cross Section in FPGA 19

Comparing Proton and Neutron Induced SEU Cross Section in FP...

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Vanat, Tomas Krizek, Filip Ferencei, Jozef Kubatova, Hana Czech Tech Univ Fac Informat Technol Dept Digital Design Prague Czech Republic Acad Sci Czech Republ Inst Nucl Phys Dept Nucl Spect Rez Czech Republic

ISBN: (纸本)9781509024674

Single event upsets (SEU) are induced by an electric charge deposited in the material of the chip. the origin of the charge can be either from outside of the chip or it can be generated inside as a result of a nuclear reaction. We have measured the cross section of SEUs in FPGA using protons (directly ionizing particles) and neutrons (indirectly ionizing particles). Used energies up to 34 MeV are in the range, where the differences in the proton's ionizing power are most significant thanks to the Bragg peak. Measurements have shown, that the direct ionization is not the dominant effect causing SEU.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Multi-Objective BDD Optimization for RRAM based Circuit design 19

Multi-Objective BDD Optimization for RRAM based Circuit Desi...

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Shirinzadeh, Saeideh Soeken, Mathias Drechsler, Rolf Univ Bremen Dept Math & Comp Sci D-28359 Bremen Germany Ecole Polytech Fed Lausanne Integrated Syst Lab Lausanne Switzerland DFKI GmbH Cyber Phys Syst Bremen Germany

ISBN: (纸本)9781509024674

Resistive switching property enables various promising applications such as design of non-volatile in-memory computing devices which has attracted high attention to Resistive Random Access Memories (RRAMs). In this work, we present a multi-objective BDD optimization approach for RRAM based logic circuit design. Dissimilar to classical BDD optimization, evaluating the cost metrics of the circuits in this case does not only depend on the number of BDD nodes but is more advanced. We have utilized a non-dominated sorting genetic algorithm for bi-objective BDD optimization with respect to the number of required RRAMs and computational steps addressing the area and delay of the resulting circuits, respectively. the algorithm also allows preference to one of the objectives if it is of higher significance. Experimental results show that the proposed multi-objective genetic algorithm achieves considerable reduction in both aforementioned criteria in comparison with an existing approach.

关键词： Computer circuits

来源：评论

学校读者我要写书评

暂无评论

Comparison of Gate-Driven and Bulk-Driven Current Mirror Topologies 19

Comparison of Gate-Driven and Bulk-Driven Current Mirror Top...

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Rakus, Matej Stopjakova, Viera Arbei, Daniel Slovak Univ Technol Bratislava Fac Elect Engn & Informat Technol Inst Elect & Photon Bratislava Slovakia

ISBN: (纸本)9781509024674

In this paper, different topologies of gate-driven and bulk-driven current mirrors designed in 90 nm CMOS technology are presented. Since the conventional MOS transistors can work as a bulk-driven device, there is no need for any modification of the existing MOSFET structure or technology process. the bulk-driven current mirror is capable of operating at power supplies down to the threshold voltage of a standard MOS device. Bulk-driven current mirror topologies were compared to their gate-driven equivalents in terms of main properties and output characteristics. the achieved results prove that the bulk-driven design technique is very promising towards ultra low-voltage analog ICs.

关键词： gate-driven bulk-driven current mirrors output resistance output swing low voltage analog circuits

来源：评论

学校读者我要写书评

暂无评论

Co-design of CML IO and Interposer Channel for Low Area and Power Signaling 19

Co-design of CML IO and Interposer Channel for Low Area and ...

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Chaudhary, Muhammad Waqas Heinig, Andy Fraunhofcr Inst Integrated Circuits IIS Design Automat Div EAS D-01069 Dresden Germany

ISBN: (纸本)9781509024674

In recent years, 2.5D integration of ICs on Inter-poser is becoming popular for highly integrated miniaturized systems. To combine two or more chips together, there is a lot of communication between the chips and this needs either a very high number of slow channels or numerous high speed channels. To find an optimum number and speed of interposer channels is an important task. In conventional PCB data communication systems, very high speed serial data transmission circuits are used which take a lot of area and power. While in 2.5D systems, area-power are strict constraints and the interposer channel is drastically different from PCB channel in terms of its electrical properties. To enable high bandwidth chip-to-chip interposer communication with low area-power requirements, it is mandatory to co-design the interposer channel and IO circuit. To address the issue, this paper discusses the electrical properties of 2.5D channel segments along with a co-design methodology targeting optimum area-power cost for maximum bandwidth current mode logic differential driver.

关键词： Bandwidth

来源：评论

学校读者我要写书评

暂无评论

A Rule-Based Approach for Minimizing Power Dissipation of Digital circuits 19

A Rule-Based Approach for Minimizing Power Dissipation of Di...

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Das, Subrata Dasgupta, Parthasarathi Fiser, Petr Ghosh, Sudip Das, Dehesh Kumar Jadavpur Univ Dept Comp Sci & Engn Kolkata India Indian Inst Management Calcutta MIS Grp Kolkata India Czech Tech Univ Fac Informat Technol Prague Czech Republic IIEST Sch VLSI Technol Sibpur Howrah India

ISBN: (纸本)9781509024674

Minimization of power dissipation of VLSI circuits is one of the major concerns of recent digital circuit design primarily due to the ever decreasing feature sizes of circuits, higher clock frequencies and larger die sizes. the primary contributors to power dissipation in digital circuits include leakage power, short-circuit power and switching power. Of these, power dissipation due to the circuit switching activity constitutes the major component. As such, an effective mechanism to minimize the power loss in such cases often involves the minimization of the switching activity. In this paper, we propose an intelligent rule-based algorithm for reducing the switching activity of the digital circuits at logic optimization stage. the proposed algorithm is empirically tested for several standard digital circuits with Synopsys EDA tool and the results obtained are quite encouraging.

关键词： Switching activity low-power VLSI circuits CMOS power dissipation dynamic power logic optimization

来源：评论

学校读者我要写书评

暂无评论

A New User-Friendly ATPG Platform for Digital circuits 19

A New User-Friendly ATPG Platform for Digital Circuits

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Lipovsky, M. Svarc, J. Gramatova, E. Fiser, P. Slovak Univ Technol Bratislava Fac Informat & Informat Technol Bratislava Slovakia Czech Tech Univ Fac Informat Technol Prague Czech Republic

ISBN: (纸本)9781509024674

the paper presents a new graphical platform for automatic test patterns generation and fault simulation for digital circuits. the platform integrates two existing academic tools for test pattern generation and fault simulation: ATALANTA and HOPE. Both tools use a specific format "bench" for circuit description which is not suitable in connection to professional CAD tools. therefore, the platform has been extended by a new translator for mapping a VHDL digital circuit model to the format "bench". the platform contains also a separate random test patterns generator linked to the fault simulator HOPE and generation of test pairs for delay faults using the transition fault model. the new automatic test pattern generation platform provides a user-friendly environment suitable for education.

关键词： digital circuits ATPG fault simulation VHDL HOPE ATALANTA

来源：评论

学校读者我要写书评

暂无评论

Precision Human Body Temperature Measurement Based on thermistor Sensor 19

Precision Human Body Temperature Measurement Based on Thermi...

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Narczyk, Pawel Siwiec, Krzysztof Pleskacz, Witold A. Warsaw Univ Technol Inst Microelect & Optoelect Ul Koszykowa 75 PL-00662 Warsaw Poland

ISBN: (纸本)9781509024674

An analog front-end, with a new temperature calibration method, for an accurate temperature measurement of a human body has been presented. the discussed AFE consists of a current reference, a precision current source, a programmable gain amplifier, a voltage source proportional to absolute temperature and on-chip temperature calibration resistor. Human body temperature can be measured in the range from +25 degrees C to +45 degrees C at the operating temperature of an IC in the range from -40 degrees C to +125 degrees C with 0.1 degrees C precision. the presented analog front-end consumes no more than 180 uW and was designed in UMC CMOS 130 nm technology.

关键词： biomedical circuits and systems human body temperature measurement skin temperature analog front-end (AFE) current reference current source programmable gain amplifier proportional to absolute temperature voltage source (PTAT) CMOS 130 nm

来源：评论

学校读者我要写书评

暂无评论

Parity Waterfall Method 19

Parity Waterfall Method

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Borecky, Jaroslav Kohlik, Martin Kubatova, Hana Czech Tech Univ Dept Digital Design Fac Informat Technol Tech 9 Prague Czech Republic

ISBN: (纸本)9781509024674

this paper proposes a method for improvement of the fault-coverage capabilities of Field Programmable Gate Array (FPGA) designs. It utilizes Concurrent Error Detection (CED) techniques and the basic architectures of actual modern FPGAs the Look-Up Table (LUT) with two outputs. Proposed Parity Waterfall method is based on a cascade (waterfall) of several waves of inner parity generating the final parity of outputs of the whole circuit. the utilization of the (mostly) unused output of a two-output LUT allows the proposed method to cover any single possible routing or LUT fault with a small area overhead. the method is experimentally evaluated using the standard set of IWLS2005 benchmarks and using our simulator/emulator. the experimental results of the proposed parity waterfall method are compared with a similar existing technique (duplication with comparison). these results show that the area overhead is smaller than the overhead of the duplication with comparison method for all of the tested circuits and 100% fault coverage is achieved.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Verification Approach Based on Emulation Technology 19

Verification Approach Based on Emulation Technology

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Koczor, Arkadiusz Matoga, Lukasz Penkala, Piotr Pawlak, Adam Evatronix SA Bielsko Biala Poland Silesian Tech Univ Inst Elect Gliwice Poland

ISBN: (纸本)9781509024674

the paper presents a scalable architecture for fast emulation of systems-on-Chip. It is implemented on a dedicated modular FPGA-based hardware platform. this verification ecosystem presents a new approach to improve efficiency of the verification process through hardware-based acceleration of tests. the system consists of dedicated hardware modules and third-party;easy-to-get evaluation boards to provide an affordable solution for SMEs with fast bring-up time for emulation purposes. By complying to many industry standards in the areas of communication interfaces, memory modules, and connectors, the presented platform acts as a cost-effective, desktop-size solution and can be used in early stages of hardware-assisted verification process. It provides a debug capability which enables quick identification and elimination of implementation bugs. the paper also reports on the use of the emulation environment in FPGA-in-the-Loop simulation. this solution may be applied to a broad range of applications.

关键词： design verification emulation platform debugging FPGA-in-the-Loop co-simulation

来源：评论

学校读者我要写书评

暂无评论

A Hybrid Power Modeling Approach to Enhance High-Level Power Models 19

A Hybrid Power Modeling Approach to Enhance High-Level Power...

引用

ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Nocua, Alejandro Virazel, Arnaud Bosio, Alberto Girard, Patrick Chevalier, Cyril Univ Montpellier CNRS LIRMM Montpellier France STMicroelectronics Grenoble France

ISBN: (纸本)9781509024674

Power management techniques are applied at high abstraction levels to reduce chip power consumption. Accurate and efficient power models are needed as early as possible in the design flow to ensure that correct saving decisions are taken. However, accuracy at those levels cannot be ensured, as there is not exact knowledge of the circuit structure. then, power models based on estimation techniques at lower abstraction levels are desired. In this work, we propose a hybrid power modeling approach based on an effective library characterization methodology and an efficient power estimation flow to accurately assess gate-level power consumption. the main idea is to enhance the high-level power models by providing realistic information of the physical design. We perform experiments on ISCAS'85 benchmark circuits synthesized with a 28nm FDSOI technology. To prove the validity of our approach, we compare our results with SPECTRE simulations and show that we can achieve a 144X speedup on the runtime with a transistor-like accuracy.

关键词： FDSOI Technology Hybrid Power Model Library Characterization Power-Aware design

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共69页 << < 13 14 15 16 17 18 19 20 21 22 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：