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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是171-180 订阅

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A General Approach for Comparing Metastable Behavior of Digital CMOS Gates 19

A General Approach for Comparing Metastable Behavior of Digi...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Polzer, thomas Steininger, Andreas TU Wien Inst Comp Engn A-1040 Vienna Austria

ISBN: (纸本)9781509024674

In digital CMOS essentially all sequential function blocks may get metastable in one way or another, when provided with marginal inputs. Most often the result is a delayed reaction at the output, which, in a synchronous design, potentially violates the timing assumptions. therefore metastable behavior is often characterized by the Mean Time Between Upset (MTBU), which reflects the expected interval between such violations on a statistical base. However, not all designs are synchronous - there are even sequential elements specifically intended for use in context with elastic timing, such as the mutual exclusion element or the Muller C-element. For these a characterization via MTBU is not useful;but on the other hand there seem to be no reasonable alternatives. therefore in this paper we propose the use of the delay graph (over the relevant quantity that causes metastability when becoming marginal) for this purpose. We elaborate its correspondence with the usual MTBU graph and the metastability parameters, namely tau and T0. As a proof of concept we apply our strategy to a set of sequential elements, like D-latch, RS-latch, Muller C-element and mutex and discuss the differences we identified.

关键词： CMOS integrated circuits

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Sequential Test Decompressors with Fast Variable Wide Spreading 19

Sequential Test Decompressors with Fast Variable Wide Spread...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Novak, O. Jenicek, J. Rozkovec, M. Tech Univ Liberec FMMIS Inst Informat Technol & Elect Liberec Czech Republic

ISBN: (纸本)9781509024674

Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test pattern decoding. the first few scan chain slices are then filled with test vectors that have lower decodability as the number of free variables is limited by the test access mechanism bandwidth. We have found that it is possible to increase the number of free variables in the equations describing the care bits encoding by fast creating and wide spreading as many as possible independent linear combinations of the tester bits and using them for the scan chain loading. We propose a decompressor combining a combinational linear decompressor and an LFSR like automaton that effectively distributes the free variables within the test pattern. the proposed test pattern decompressor outperforms the decodability of other decompressors with similar hardware overhead and it reduces the test time due to a possible reduction of the decompressor preloading.

关键词： integrated circuit design design for testability (DFT) scan-based test linear finite state machines test application time reduction test data compression hardware-based test vector linear-decompression scheme

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BioSoC: Highly Integrated System-on-Chip for Health Monitoring 19

BioSoC: Highly Integrated System-on-Chip for Health Monitori...

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ieee 19th International symposium on design and diagnostics of electronic circuits & systems (DDECS)

作者： Siwiec, Krzysztof Marcinek, Krzysztof Boguszewicz, Piotr Borejko, Tomasz Halauko, Aleh Jarosz, Adam Kopanski, Jakub Kurjata-Pfitzner, Ewa Narczyk, Pawel Plasota, Maciej Wielgus, Andrzej Pleskacz, Witold A. Warsaw Univ Technol Inst Microelect & Optoelect Ul Koszykowa 75 PL-00662 Warsaw Poland Inst Electr Mat Technol Al Lotnikow 32-46 PL-02668 Warsaw Poland

ISBN: (纸本)9781509024674

the BioSoC is a highly integrated SoC that consists of analog front-ends, analog to digital converters and a 32-bit microcontroller - Adelite. the designed IC allows for dynamic acquisition and processing of the most important human physiological parameters. the provided analog interfaces to external electrodes and sensors allow measurement of electrocardiograms (ECG), electromyograms (EMG), skin temperature and resistance, and respiration rate (RR). After analog processing signals are sampled and digitized in analog-to-digital converters they can be further processed in a 32-bit microcontroller Adelite. the clock frequency of the microprocessor core is configurable from 32 kHz up to 16 MHz. the microcontroller is equipped with many digital interfaces and peripherals, such as 2xUART and 2xSPI with DMA channels, 16 GPIOs and S timers along with RTC. the BioSoC makes it possible to build highly integrated devices with rich functionalities in the area of telemedicine that respond to the growing demand for portable health monitoring. the BioSoC was designed and fabricated in UMC CMOS 130 nm technolo*, process and occupies the area of 25mm(2).

关键词： System on Chip (SoC) biomedical circuits and systems electrocardiogram (ECG) electromyogram (EMG) skin resistance skin temperature respiration rate (RR) analog front-end (AFE) microprocessor microcontroller telemedicine physiological health acquisition processing monitoring CMOS

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design for Test and Diagnosis of Power Switches

Design for Test and Diagnosis of Power Switches

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18th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS 2015)

作者： Valka, Miroslav Bosio, Alberto Dilillo, Luigi Girard, Patrick Virazel, Arnaud Debaud, Philippe Guilhot, Stephane Grenoble Alpes Univ TIMA Lab Grenoble France Univ Montpellier LIRMM Lab F-34059 Montpellier France ST Microelect Grenoble France

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. the proposed approach has been validated through SPICE simulations on ITC'99 benchmark circuits as well as on industrial test cases.

关键词： design for test and diagnosis low power design power gating power switches

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An Early Stage design Flow for Switching Noise Attenuation

An Early Stage Design Flow for Switching Noise Attenuation

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18th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS 2015)

作者： Zeidler, Steffen Fan, Xin Schrape, Oliver Krstic, Milos IHP Technol Pk 25 D-15236 Frankfurt Oder Germany

In the design of highly complex integrated circuits (ICs), switching noise is a raising problem. To handle this, current shaping techniques are applied to reduce current peaks causing ground bounce and voltage drops. Such techniques distribute the switching activity by adding phases and/or jitter to the clock of different domains. However, they are usually performed at later phases of the design process, i.e., in the chip layout. In this phase, the timing margins of the logic paths are typically fixed, which limit the clock phases that can be introduced between the domains. In this paper, we present a novel design preconditioning flow, which addresses the optimization of power noise characteristics of a design already at the frontend level. this allows early RTL-level design modifications, e.g., clock inversion or pipeline stage insertion, which potentially facilitate noise mitigation or enhance clock skewing in later design stages.

关键词： Switching noise low-noise circuits design preconditioning current shaping power optimization

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An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors

An Asynchronous Summation Circuit for Noise Filtering in Sin...

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18th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS 2015)

作者： Yang, Xiao Zhu, Hongbo Nakura, Toru Iizuka, Tetsuya Asada, Kunihiro Univ Tokyo Dept Elect Engn & Informat Syst Tokyo Japan Univ Tokyo VLSI Design & Educ Ctr VDEC Tokyo Japan

An asynchronous projection and summation circuit is proposed for single photon avalanche diode (SPAD) sensors. thanks to the efficient interconnection by the asynchronous technique, the circuit can be easily implemented inside 2D SPAD arrays. As a result, the precise summation of the 1b data in one row can be parallel processed for all rows within the same cycle. A test-of-concept chip was fabricated in a 0.18 mu m 1P5M CMOS process. By measurement results, the summation of a 15-pixel row can be achieved by the proposed circuit within 20.5 ns. Such a speed is very important for SPAD-based sensors that need fast summation operations.

关键词： Single photon avalanche diode in-pixel processing asynchronous circuit

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Non-Cyclic design Space Exploration for ASIPs - Compiler-Centered Microprocessor design (CoMet)

Non-Cyclic Design Space Exploration for ASIPs - Compiler-Cen...

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18th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS 2015)

作者： Urban, Roberto Vierhaus, Heinrich T. Schoelzel, Mario Altmann, Enrico Seelig, Horst BTU Cottbus Senftenberg Postfach 101344 D-03046 Cottbus Germany IHP GmbH Technol Pk 25 D-15236 Frankfurt Oder Germany GED Elect Design GmbH Technol Pk 27 D-15236 Frankfurt Oder Germany

the CoMet approach on designing application specific instruction set processors (ASIPs) is targeting a non-cyclic design space exploration (DSE). the design process is driven by a step by step refinement of intermediate codes, known from compiler backends. In every step, the intermediate code can be simulated and profiled. Based on that profiling information, it can be further transformed to an optimized or refined intermediate code. the whole transformation process is implemented in a GUI-based design tool, whose main component is a configurable simulator for intermediate codes. It will be shown how the configurable intermediate code simulator is used and how the intermediate code transformation and the VHDL generation of the ASIP model will work in the CoMet tool.

关键词： ASIP design design space exploration CoMet intermediate codes compiler-driven design VHDL generation

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Investigation of Intermittent Resistive Faults in Digital CMOS circuits

Investigation of Intermittent Resistive Faults in Digital CM...

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18th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS 2015)

作者： Kerkhoff, Hans G. Ebrahimi, Hassan Univ Twente Ctr Telemat & Informat Technol Testable Design & Test Integrated Syst TDT Grp POB 217 NL-7500 AE Enschede Netherlands

No fault found (NFF) is a major threat in extremely dependable high-end process node integrated systems, in e.g., avionics. One category of NFFs is the intermittent resistive fault (IRF), often originating from bad (e.g., via- or TSV-based) interconnections. this paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g., one month, while the duration of the defect can be as short as 50 ns, thus to evoke and detect these faults is a huge scientific challenge. Two methods to detect short pulses induced by IRFs are proposed. To improve the task of maintenance of avionics and reduce the current high debugging costs, an on-chip data logging system with time stamp and stored environmental conditions is introduced. Finally, a hardware implementation of an IRF generator is presented.

关键词： Dependability reliability no faults found intermittent resistive faults evoking & detection of intermittent faults

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Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated circuits

Digital Embedded Test Instrument for On-Chip Phase Noise Tes...

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18th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS 2015)

作者： Azais, Florence David-Grignot, Stephane Latorre, Laurent Lefevre, Francois Univ Montpellier CNRS LIRMM 161 Rue Ada F-34095 Montpellier France NXP Semicond 2 Espl Anton Phillips F-14000 Caen France

this paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. the technique relies on 1-bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140nm technology occupies only 7,885 mu m(2), which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument.

关键词： Noise measurement phase noise analog/IF signals 1-bit acquisition digital signal processing built-in-self-test BIST test cost reduction

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Analyzing Inconsistencies in UML/OCL Models

Analyzing Inconsistencies in UML/OCL Models

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18th ieee International symposium on design and diagnostics of electronic circuits and systems (DDECS 2015)

作者： Przigoda, Nils Wille, Robert Drechsler, Rolf Univ Bremen Grp Comp Architecture D-28359 Bremen Germany Johannes Kepler Univ Linz Inst Integrated Circuits A-4040 Linz Austria DFKI GmbH Cyber Phys Syst D-28359 Bremen Germany

Modeling languages such as the unified modeling language (UML) or the systems modeling language (SysML) in combination with constraint languages such as the object constraint language (OCL) allows for an abstract description of a system prior to its implementation. But the resulting system models can be highly non-trivial and, hence, errors in the descriptions can easily arise. In particular, too strong restrictions leading to an inconsistent model are common. Motivated by this, researchers and engineers developed methods for the validation and verification of given formal models. However, while these methods are efficient to detect the existence of an inconsistency, the designer is usually left alone to identify the reasons for it. In this contribution, we propose an automatic method which efficiently determines reasons explaining the contradiction in an inconsistent UML/OCL model. For this purpose, all constraints causing the contradiction are comprehensibly analyzed. By this, the designer is aided during the debugging of his/her model.

关键词： UML/OCL models inconsistent models contradiction analysis debugging

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