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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是11-20 订阅

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Supporting analog design for reliability by efficient provision of reliability information to designers 26

Supporting analog design for reliability by efficient provis...

引用

26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Gonzalez, Fabio A. Velarde Hahne, Lukas Ortstein, Katrin Lange, Andre Crocoll, Sonja Fraunhofer Inst Integrated Circuits IIS Div Engn Adapt Syst EAS Dresden Germany X FAB Dresden GmbH & Co KG Dresden Germany

ISBN: (纸本)9798350332773

Multiple degradation mechanisms limit the lifetime of integrated circuits (ICs). Different aspects can be tackled with design for Reliability approaches already during circuit design to avoid serious implications of degradation for ICs in the field. For example, aging simulations can be performed to investigate the impact of the degradation of integrated transistors onto circuit performance. Since these simulations cause a significant verification effort, we work on approaches to efficiently feed reliability information back to circuit designers. this article discusses these approaches with their application scenarios and benefits.

关键词： IC reliability transistor degradation design support mission profile

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Co-design of Photonic IC, electronic IC, and Interposer for 1.6 Tbps O/E Converter in Active Optical Package 13

Co-Design of Photonic IC, Electronic IC, and Interposer for ...

引用

13th ieee CPMT symposium Japan

作者： Matsui, Naoki Noriki, Akihiro Kuwatsuka, Haruhiko Nakamura, Fumi Suda, Satoshi Kurosu, Takayuki Amano, Takeru Ishikawa, Satoshi Yoshikawa, Hiromichi Motoji, Rcona Maeda, Dan Uemura, Hirotaka KYOCERA Corp Yokohama Kanagawa Japan Natl Inst Adv Ind Sci & Technol Tsukuba Ibaraki Japan

We have developed a design methodology for a compact and high-speed optical/electrical converter for active optical package through co-design of a photonic integrated circuit and electronic integrated circuits, assemb... 详细信息

ISBN: (纸本)9798350377828;9798350377811

关键词： Silicon photonics Active Optical Package co-design interposer

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An Efficient Approach for STLs Development of Automotive SoCs Using Colored Petri Nets 27

An Efficient Approach for STLs Development of Automotive SoC...

引用

27th International symposium on design & diagnostics of electronic circuits & systems (DDECS)

作者： Castillo, Ernesto Cristopher Villegas da Silva, Felipe Augusto Glass, Michael Cadence Design Syst Munich Germany Ulm Univ Inst Embedded Syst Real Time Syst Ulm Germany

ISBN: (纸本)9798350359343

One of the biggest concerns of Automotive System--on-Chip (SoC) design is the strict safety requirements for their hazardous operative scenarios. Commonly, designers employ Safety Mechanisms (SMs) to mitigate the fault effects and improve the SoC's safety levels. During the development phases, metrics, such as the Fault coverage (FC), are used to validate the effectiveness of the SMs. However, achieving such metrics, as defined by automotive standards, demands additional verification steps, resorting to extensive Fault Injection (FI) campaigns. these usually require mature design stages (e.g., RT-Gate level) involving significant simulation times and several iterations until obtaining the desired FC. therefore, there is a high demand for new methodologies enabling FC estimation, supporting earlystage exploration, and avoiding expensive redesign phases. this work proposes a methodology exploiting Colored Generalized Stochastic Petri Nets (CGSPN) to model the SoC's architecture at a high level for FC estimation. the method optimizes and reduces the FI campaigns and is intended as a powerful tool supporting the development cycles of SMs, e.g., Software Test Libraries (STLs). Our experiments on an automotive test case indicate that STLs can be validated at a high level with minimal accuracy loss (1.1% on average) by optimizing the fault list in 28%. the results also showed a meaningful speed-up of up to 160x in the development process of STLs.

关键词： Automotive Fault Injection Fault Coverage Petri Nets

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Structured design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations 26

Structured Design and Evaluation of a Resistor-Based PUF Rob...

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26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Riehm, Carl Frisch, Christoph Burcea, Florin Hiller, Matthias Pehl, Michael Brederlow, Ralf Tech Univ Munich TUM Sch Computat Informat & Technol Munich Germany Fraunhofer AISEC Garching Germany

ISBN: (纸本)9798350332773

this paper proposes a new fully CMOS-compatible PUF primitive robust against process variations, supply voltage variations and temperature drift (PVT) based on resistive structures that implements advanced compensation mechanisms already on circuit level. Based on analog simulation data, the PUF is evaluated regarding its unpredictability and its reliability. the results indicate a high quality. Further, a structured approach for designing a suitable error correction is presented to illustrate the whole PUF system.

关键词： Silicon PUF error orrection mixed signal

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Embedded Tutorial - RRAMs: How to Guarantee their Quality Test after Manufacturing? 26

Embedded Tutorial - RRAMs: How to Guarantee Their Quality Te...

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26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Poehls, L. M. Bolzani Rhein Westfal TH Aachen Aachen Germany

ISBN: (纸本)9798350332773

the use of Resistive Random Access Memories (RRAMs) for implementing emerging applications depends not only on being able to properly test them after manufacturing, but also being able to guarantee their reliability during lifetime. these novel non-volatile memories can be affected by manufacturing deviations, process variation and defects, as well as by time-dependent deviations, environmental and temporal variations. In this context, this tutorial aims to introduce the main sources of reliability issues at time zero and during lifetime, highlighting the challenges related to properly identify manufacturing failure mechanisms and consequently, the deviation of more accurate fault models. In addition, this tutorial aims to summarize the state-of-the-art regarding manufacturing test strategies and provide a discussion about the key challenges of testing RRAMs at time zero. Finally, this tutorial provides information about how to increase the efficiency of manufacturing test strategies in order to avoid test escapes, which can compromise RRAM's reliability during lifetime.

关键词： RRAMs Sources of Reliability Issues Manufacturing Test Strategies Stress Conditions

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Evaluating the Hardware Performance Counters of an Xtensa Virtual Prototype 26

Evaluating the Hardware Performance Counters of an Xtensa Vi...

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26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Omotosho, Adebayo Iiahi, Sirine Castillo, Ernesto Cristopher Villegas Hammer, Christian Sauer, Christian Univ Cent Lancashire Preston Lancs England Univ Passau Passau Germany Cadence Design Syst Munich Germany

ISBN: (纸本)9798350332773

Embedded systems' hardware and software stacks are becoming more complex requiring more development time, time to market, and cost, which contributes to delayed delivery of these silicon devices. A virtual prototype (VP) provides an embedded systems architecture simulator for application development and testing purposes. In this paper, we developed and present the first virtual prototype of the Xtensa LX7 microprocessor that evaluates the performance of its emulated hardware performance counters (HPCs) with those collected from an actual Xtensa LX7 hardware. Seven machine learning models were developed and trained to find the relationships between the two different datasets for the sample application of classifiying return-oriented programming (ROP) attacks. Our experiments show that the obtained micro-architectural characteristics on the VP are on average about 70% similar and thus permit early simulation capabilities for developers and testers.

关键词： virtual prototype xtensa hardware performance counters return oriented programming machine learning

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MODEE-LID: Multiobjective design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers 26

MODEE-LID: Multiobjective Design of Energy-Efficient Hardwar...

引用

26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Hurta, Martin Mrazek, Vojtech Drahosova, Michaela Sekanina, Lukas Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9798350332773

Taking levodopa, a drug used to treat symptoms of Parkinson's disease, is often connected with severe side effects, known as Levodopa-induced dyskinesia (LID). It can fluctuate in severity throughout the day and thus is difficult to classify during a short period of a physician's visit. A low-power wearable classifier enabling long-term and continuous LID classification would thus significantly help with LID detection and dosage adjustment. this paper deals with an automated design of energy-efficient hardware accelerators of LID classifiers that can be implemented in wearable devices. the accelerator consists of a feature extractor and a classification circuit co-designed using genetic programming (GP). We also introduce and evaluate a fast and accurate energy consumption estimation method for the target architecture of considered classifiers. In a multiobjective design scenario, GP evolves solutions showing the best trade-offs between accuracy and energy. Compared to the state-of-the-art solutions, the proposed method leads to classifiers showing a comparable accuracy while the energy consumption is reduced by 49 %.

关键词： levodopa-induced dyskinesia energy efficient hardware accelerator multiobjective design

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Split-Et-Impera: A Framework for the design of Distributed Deep Learning Applications 26

Split-Et-Impera: A Framework for the Design of Distributed D...

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26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Capogrosso, Luigi Cunico, Federico Lora, Michele Cristani, Marco Fummi, Franco Quaglia, Davide Univ Verona Dept Comp Sci Verona Italy

ISBN: (纸本)9798350332773

Many recent pattern recognition applications rely on complex distributed architectures in which sensing and computational nodes interact together through a communication network. Deep neural networks (DNNs) play an important role in this scenario, furnishing powerful decision mechanisms, at the price of a high computational effort. Consequently, powerful state-of-the-art DNNs are frequently split over various computational nodes, e.g., a first part stays on an embedded device and the rest on a server. Deciding where to split a DNN is a challenge in itself, making the design of deep learning applications even more complicated. therefore, we propose Split-Et-Impera, a novel and practical framework that i) determines the set of the best-split points of a neural network based on deep network interpretability principles without performing a tedious try-and-test approach, ii) performs a communication-aware simulation for the rapid evaluation of different neural network rearrangements, and iii) suggests the best match between the quality of service requirements of the application and the performance in terms of accuracy and latency time.

关键词： Deep Neural Networks Split Computing System-Level design Communication Networks Simulation

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Prediction of Inference Energy on CNN Accelerators Supporting Approximate circuits 26

Prediction of Inference Energy on CNN Accelerators Supportin...

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26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Pinos, Michal Mrazek, Vojtech Sekanina, Lukas Brno Univ Technol Brno Czech Republic

ISBN: (纸本)9798350332773

design methodologies developed for optimizing hardware implementations of convolutional neural networks (CNN) or searching for new hardware-aware neural architectures rely on the fast and reliable estimation of key hardware parameters, such as the energy needed for one inference. Utilizing approximate circuits in hardware accelerators of CNNs faces the designers with new problems during their simulation commonly used tools (TimeLoop, Accelergy, Maestro) do not support approximate arithmetic operations. this work addresses the fast and efficient prediction of consumed energy in hardware accelerators of CNNs that utilize approximate circuits such as approximate multipliers. First, we extend the state-of-the-art software frameworks TimeLoop and Accelergy to predict the inference energy when exact multipliers are replaced with various approximate implementations. the energies obtained using the modified tools are then considered the ground truth (reference) values. then, we propose and evaluate, using two accelerators (Eyeriss and Simba) and two types of networks (CNNs generated by EvoApproxNAS and standard ResNet CNNs), two predictors of inference energy. We conclude that a simple predictor based on summing the energies needed for all multiplications highly correlates with the reference values if the CNN's architecture is fixed. For complex CNNs with variable architectures typically generated by neural architecture search algorithms, a more sophisticated predictor based on a machine learning model has to be employed. the proposed predictors are 420-533x faster than reference solutions.

关键词： Timing circuits

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A Reliability-aware Environment for design Exploration for GPU Devices 26

A Reliability-aware Environment for Design Exploration for G...

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26th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Sierra, Robert Limas Guerrero-Balaguera, Juan-David Condia, Josie E. Rodriguez Reorda, Matteo Sonza Politecn Torino Dept Control & Comp Engn DAUIN Turin Italy

ISBN: (纸本)9798350332773

Nowadays, GPU platforms have gained wide importance in applications that require high processing power. Unfortunately, the advanced semiconductor technologies used for their manufacturing are prone to different types of faults. Hence, solutions are required to support the exploration of the resilience to faults of different architectures. Based on this motivation, this work presents an environment dedicated to the analysis of the impact of permanent faults on GPU platforms. this environment is based on GPGPU-Sim, with the objective of exploiting the configuration features of this tool and, thus, analyzing the effects of faults when changing the target architecture. To validate the environment and show its usability, a fault campaign has been carried out where three different GPU architectures (Kepler, Volta, and Turing) were used. In addition, each GPU has been modified with an arbitrary number of parallel processing cores (or SMs). three representative applications (Vector Add, Scalar Product, and Matrix Multiply) were executed on each GPU, and the behavior of each architecture in the presence of permanent faults in the functional (i.e., integer unit and floating-point) units was analyzed. this fault campaign shows the usability of the environment and demonstrates its potential use to support decisions on the best architectural parameters for a given application.

关键词： Architectural models design exploration Graphics Processing Units (GPUs) Permanent faults Reliability

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