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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Intermittent Resistive Faults in Digital CMOS circuits 18

Intermittent Resistive Faults in Digital CMOS Circuits

引用

ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kerkhoff, Hans G. Ebrahimi, H. Univ Twente Ctr Telemat & Informat Technol CTIT Testable Design & Test Integrated Syst TDT Grp Enschede Netherlands

ISBN: (纸本)9781479967803

A major threat in extremely dependable high-end process node integrated systems in e.g. avionics are no failures found (NFF). One category of NFFs is the intermittent resistive fault, often originating from bad (e.g. via- or TSV-based) interconnections. this paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g. one month, while the duration of the defect can be as short as 50 nanoseconds, to evoke and detect these faults is a huge scientific challenge. An on-chip data logging system with time stamp and stored environmental conditions, along with the detection, will drastically improve the task of maintenance of avionics and reduce the current high debugging costs.

关键词： Dependability Reliability No Faults Found Intermittent Resistive Faults Evoking & Detection of Intermittent Faults

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A design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm 18

A Design for the 178-MHz WXGA 30-fps Optical Flow Processor ...

引用

ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Matsumura, Tetsuya Kurokawa, Aoi Imamura, Kousuke Matsuda, Yoshio Nihon Univ Coll Engn Koriyama Fukushima Japan Kanazawa Univ Coll Sci & Engn Kanazawa Ishikawa Japan

ISBN: (纸本)9781479967803

We propose an optical flow processor, which allows real-time processing of WXGA 30-fps at 178.3 MHz. By introducing the SOR method and a pipeline operation for the Gauss-Seidel method to the iterative flow calculation, computational complexity can be reduced to 14.5% when compared to the previous HOE processor. We decreased the area of the embedded memory by using the image division method, applying line memory, and optimizing the computation word length. the core size of the designed processor is 16.82 mm(2) in 90 nm process technology, which is approximately 5% of the previous HOE processor. the processor can operate completely in parallel, which ensures high-resolution scalability.

关键词： HOE optical flow processor scalability

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Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible circuits. 18

Boolean Difference Technique for Detecting All Missing Gate ...

引用

ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Mondal, Joyati Mondal, Bappaditya Kole, Dipak Rahaman, Hafizur KDas, Debesh Jadavpur Univ Dept Comp Sci & Engg Kolkata 32 India Indian Inst Engn Sci & Technol Dept Comp Sci & Engg Sibpur India

ISBN: (纸本)9781479967803

Quantum reversible circuit is a new emerging technology attracting the researchers. A reversible circuit is composed of reversible gates only. A reversible Toffoli gate has two components - the control and the target. the missing gate fault model is used for modelling defects in quantum k-CNOT gate. this work introduces Boolean Difference technique for deriving the test set for detecting all faults in a reversible circuit implemented with k-CNOT gates. then a optimizing algorithm is used to derive optimal test set to detect all possible partial missing faults in a circuit.

关键词： Missing-gate fault quantum computing reversible logic test generation

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An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors 18

An Asynchronous Projection and Summation Circuit for In-Pixe...

引用

ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Yang, Xiao Zhu, Hongbo Nakura, Toru Iizuka, Tetsuya Asada, Kunihiro Univ Tokyo Dept Elect Engn & Informat Syst Tokyo Japan Univ Tokyo VLSI Design & Educ Ctr VDEC Tokyo Japan

ISBN: (纸本)9781479967803

An asynchronous projection and summation circuit is proposed for single photon avalanche diode (SPAD) sensors. thanks to the efficient interconnection by the asynchronous technique, the circuit can be easily implemented inside 2D SPAD arrays. As a result, the precise summation of the 1b data in one row can be parallel processed for all rows within the same cycle. A test-of-concept chip was fabricated in a 1P5M 0.18 mu m CMOS process. By measurement results, the summation of a 15-pixel row can be achieved by the proposed circuit within 22 ns. Such a speed is very important for SPAD-based sensors that need fast summation operations.

关键词： Asynchronous circuits Full pixels parallel processing

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Performance enhancement of serial based FPGA probabilistic fault emulation techniques 18

Performance enhancement of serial based FPGA probabilistic f...

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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Mot, Ioana Boncalo, Oana Amaricai, Alexandru Univ Politehn Timisoara Comp Engn Dept Timisoara Romania

ISBN: (纸本)9781479967803

Serial based FPGA fault emulation schemes for probabilistic errors rely on a random number generator - which is used for generation of fault bits - and a shift register - used for placing the fault bits to their corresponding fault location. It has two advantages with respect to parallel solutions: lower cost and better accuracy. the main disadvantage is represented by the high emulation overhead: for each emulation clock cycle, a number of clock cycles equal to the number of fault locations is required to load the shift register. this paper presents a technique for FPGA probabilistic fault emulation which reduces the emulation overhead, at the expense of accuracy. It is based on pseudo-random permutations within the shift register, while maintaining the number of active fault bits. We obtain a performance improve of one order of magnitude, while we have a cost increase of 27% and lower fault modeling accuracy.

关键词： FPGA fault emulation probabilistic faults sub-powered circuits

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Power-Management Specification in SystemC 18

Power-Management Specification in SystemC

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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Macko, Dominik Jelemenska, Katarina Cicak, Pavel Slovak Univ Technol Bratislava Fac Informat & Informat Technol Bratislava Slovakia

ISBN: (纸本)9781479967803

Power consumption is the greatest concern in current highly-integrated hardware-system design. the power reduction is targeted mostly through power management, implementing such techniques as clock gating, power gating, or voltage and frequency scaling. Due to growing complexity, the start-point in the design has moved from the register-transfer level to the system level. However, the power management lacks the abstraction needed for the system level. Also, different power-management techniques are specified differently, complicating the specification even more. this paper targets the unified specification of power-management techniques early in the design flow. SystemC is used for describing the system functionality along with the power management. Efficiency of the proposed approach is illustrated by comparison of the unified power- management specification and the standardized approach.

关键词： design low power power control power management power reduction system level

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2013 ieee 16th International symposium on design and diagnostics of electronic circuits & systems (DDECS) [Copyright notice]

2013 IEEE 16th International Symposium on Design and Diagnos...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to ieee Copyrights Manager, ieee Operations Center, 445 Hoes Lane, Piscataway, NJ 08854. All rights reserved. Copyright (c) 2013 by ieee. ieee Catalog Number: CFP13DDE-ART. ISBN: 978-1-4673-6136-1.

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LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs 18

LFSR Reseeding Based Test Compression Respecting Different C...

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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Novak, Ondrej Jenicek, Jiri Rozkovec, Martin Tech Univ Liberec Inst Informat Technol & Elect Liberec Czech Republic

ISBN: (纸本)9781479967803

the paper discusses possibilities of rearranging test decompressor internal structure and linking its outputs with the parallel scan chain inputs in order to obtain better compression efficiency while the hardware overhead is not increased. We have experimentally verified that the controllability of decompressor outputs can be used as a simple and easily computable measure of the decompressor efficiency. Based on this observation we have developed a procedure that chooses a suboptimal LFSR outputs and parallel scan chain inputs interconnection. the procedure proposes a permutation of the scan chain inputs so that the scan chains that are fed with patterns with higher number of care bits are linked with the highly controllable decompressor outputs. We have experimentally verified on the benchmark circuits that adopting the proposed strategy improves the compression efficiency.

关键词： design for testability (DFT) scan-based test linear finite state machines manufacturing test test application time reduction test data volume compression

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design flow for radhard TMR Flip-Flops 18

Design flow for radhard TMR Flip-Flops

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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Petrovic, Vladimir Krstic, Milo IHP Tech Pk 25 D-15236 Frankfurt Oder Germany

ISBN: (纸本)9781479967803

Protection against radiation effects in digital ASICs chip can be achieved using different design approaches. One of the popular approaches for increasing the reliability is the hardware triplication. However, the hardware triplication does not mean that the susceptibility to radiation effects can be automatically overcome. the automatic random placement of standard cells can result in higher power consumption and more occupied silicon area), with marginal improvement of the linear energy transfer threshold (LET) value. Additionally, the TMR approach usually requires changes in the standard ASIC design flow, even requesting significant modifications of the RTL code. In this paper, we will investigate the issues of design flow for TMR flip-flops, addressing both the issues of compliance to the standard ASIC design methodology, enabling the use of non-modified RTL code, as well as the layout generation of radhard TMR flip-flops, based on standard non-hardened flip-flop components.

关键词： Single event effect fault tolerance triple modular redundancy ASIC design flow radiation effects radhard design

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Compiler-Centred Microprocessor design (CoMet) From C-Code to a VHDL Model of an ASIP 18

Compiler-Centred Microprocessor Design (CoMet) From C-Code t...

引用

ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Urban, Roberto Schoelzel, Mario Vierhaus, Heinrich T. Altmann, Enrico Seelig, Horst BTU Cottbus Senftenberg Cottbus Germany IHP Frankfurt Oder Germany GED Elect Design GmbH Frankfurt Oder Germany

ISBN: (纸本)9781479967803

this paper proposes a new approach on designing application specific instruction set processors (ASIP). the design process is driven by a step by step refinement of intermediate codes, known from compiler backends. In every step the intermediate code can be simulated, and profiled. Based on profiling information it can be further transformed to an optimized or refined intermediate code. the whole transformation process is implemented in a GUI-based design tool, named CoMet, whose main component is a configurable simulator for intermediate codes. It will be shown how the configurable intermediate code simulator is used, and how the intermediate code transformation and the generation of a VHDL of the ASIP model will work in the CoMet tool.

关键词： ASIP design design space exploration CoMet intermediate codes compiler-driven design VHDL generation

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