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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Lopacinski, Lukasz Nolte, Joerg Buechner, Steffen Brzozowski, Marcin Kraemer, Rolf Brandenburg Tech Univ Cottbus Cottbus Germany IHP Frankfurt Oder Germany

ISBN: (纸本)9781479967803

transmission efficiency is an interesting topic for data link layer developers. the overhead of protocols and coding should be reduced to a minimum. this maximizes a link throughput. this is especially important for high-speed networks, where a small degradation of efficiency will degrade the throughput by several Gbps. We describe a redundancy-balancing algorithm for an adaptive hybrid automatic repeat request with Reed-Solomon coding. We introduce a testing environment, most important technical issues, and results generated on a field programmable gate array. the hybrid automatic repeat request and Reed-Solomon algorithms are explained. We provide a mathematical description, and a block diagram of the adaptation algorithm. All necessary algorithm simplifications are explained in details. the algorithm can be represented by basic operations in hardware. In most cases, it finds the optimal coding for a predefined bit error rate.

关键词： 100Gbps data link layer forward error correction FPGA hybrid ARQ reed-solomon

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design of Wireless Sensor Network for Real-Time Structural Health Monitoring 18

Design of Wireless Sensor Network for Real-Time Structural H...

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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Giammarini, Marco Isidori, Daniela Concettoni, Enrico Cristalli, Cristina Fioravanti, Matteo Pieralisi, Marco Locc Grp Via Fiume 16 I-60030 Ancona Italy Univ Politecn Marche Dipartimento Ingn Informaz I-60131 Ancona Italy

ISBN: (纸本)9781479967803

During its whole service life, a building can be subjected to operational and environmental forces usually present, or to episodic seismic loadings (earthquakes). An automated smart building is a house capable of self-monitoring in order to signal the need of maintenance, when a reduction in performance levels is detects, or to signal the need of action if there are some structural problems. One of the most important issues in civil engineering is the detection of structural damages. the flexibility of the monitoring system is fundamental, expecially in case of existing buildings. For these reasons the adoption of wireless sensor networks with different nodes is desiderable in order to monitor conditions like seismic activity. this work propose a sensor node, based on ARM microcontroller, ieee 802.15.4 wireless communication and GPS syncronization, for a wireless sensor network that solve a critical aspect in this kind of application: syncronism, when one has to collect dynamic input. Finally the paper shows the preliminary results obtained in laboratory.

关键词： dynamic analysis earthquakes structural damages Structural Health Monitoring Wireless Sensor Network

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Parameterized critical path selection for delay fault testing 18

Parameterized critical path selection for delay fault testin...

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ieee 18th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Siebert, Miroslav Gramatova, Elena Slovak Univ Technol Bratislava Fac Informat & Informat Technol Ilkovicova 2 Bratislava 84216 Slovakia

ISBN: (纸本)9781479967803

Delay faults testing is more and more important due to huge number of gates and lines integrated on a chip. Path delay faults are tested via selected critical paths in a tested digital circuit. the critical paths can be specified e.g. by static timing analysis (STA), statistical static timing analysis (SSTA) and others. Signal delay propagation is also affected by many factors such as power supply noise, multiple input switching, temperature and others during test. the impact of each factor to the path delay faults has been individually solved and published in some papers but their joint effects should be also investigated. A new technique for evaluation of critical paths and a general system for critical paths selection PaCGen have been developed and they are presented in the paper. It is based on STA and influences of multiple factors defined by the new technique for path criticality calculation. Some critical paths can be found as untestable based on structure of the circuit. the proposed system includes more effective DFT technique to change untestable critical paths to testable. Evaluation of the proposed technique has been done over ISCAS-89 benchmark circuits and compared with published results.

关键词： digital circuits delay faults path delay faults critical path path criticality design-for-testability

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design for Test and Diagnosis of Power Switches

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JOURNAL OF circuits systems AND COMPUTERS 2016年第3期25卷 1640013-1640013页

作者： Valka, Miroslav Bosio, Alberto Dilillo, Luigi Girard, Patrick Virazel, Arnaud Debaud, Philippe Guilhot, Stephane Grenoble Alpes Univ TIMA Lab Grenoble France Univ Montpellier LIRMM Lab F-34059 Montpellier France ST Microelect Grenoble France

Power gating techniques have been adopted so far to reduce the static power consumption of integrated circuits (ICs). Power gating is usually implemented by means of several power switches (PSs). Manufacturing defects affecting PSs can lead to increase in the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. thus, efficient test and diagnosis solutions are needed. In this paper, we present a novel design for Test and Diagnosis (DfTD) solution able to increase the test quality and diagnosis accuracy of PSs. the proposed approach has been validated through SPICE simulations on ITC'99 benchmark circuits as well as on industrial test cases.

关键词： design for test and diagnosis low power design power gating power switches

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An Early Stage design Flow for Switching Noise Attenuation

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JOURNAL OF circuits systems AND COMPUTERS 2016年第3期25卷 1640022-1640022页

作者： Zeidler, Steffen Fan, Xin Schrape, Oliver Krstic, Milos IHP Technol Pk 25 D-15236 Frankfurt Oder Germany

In the design of highly complex integrated circuits (ICs), switching noise is a raising problem. To handle this, current shaping techniques are applied to reduce current peaks causing ground bounce and voltage drops. Such techniques distribute the switching activity by adding phases and/or jitter to the clock of different domains. However, they are usually performed at later phases of the design process, i.e., in the chip layout. In this phase, the timing margins of the logic paths are typically fixed, which limit the clock phases that can be introduced between the domains. In this paper, we present a novel design preconditioning flow, which addresses the optimization of power noise characteristics of a design already at the frontend level. this allows early RTL-level design modifications, e.g., clock inversion or pipeline stage insertion, which potentially facilitate noise mitigation or enhance clock skewing in later design stages.

关键词： Switching noise low-noise circuits design preconditioning current shaping power optimization

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An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors

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JOURNAL OF circuits systems AND COMPUTERS 2016年第3期25卷

作者： Yang, Xiao Zhu, Hongbo Nakura, Toru Iizuka, Tetsuya Asada, Kunihiro Univ Tokyo Dept Elect Engn & Informat Syst Tokyo Japan Univ Tokyo VLSI Design & Educ Ctr VDEC Tokyo Japan

An asynchronous projection and summation circuit is proposed for single photon avalanche diode (SPAD) sensors. thanks to the efficient interconnection by the asynchronous technique, the circuit can be easily implemented inside 2D SPAD arrays. As a result, the precise summation of the 1b data in one row can be parallel processed for all rows within the same cycle. A test-of-concept chip was fabricated in a 0.18 mu m 1P5M CMOS process. By measurement results, the summation of a 15-pixel row can be achieved by the proposed circuit within 20.5 ns. Such a speed is very important for SPAD-based sensors that need fast summation operations.

关键词： Single photon avalanche diode in-pixel processing asynchronous circuit

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Investigation of Intermittent Resistive Faults in Digital CMOS circuits

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JOURNAL OF circuits systems AND COMPUTERS 2016年第3期25卷 1640023-1640023页

作者： Kerkhoff, Hans G. Ebrahimi, Hassan Univ Twente Ctr Telemat & Informat Technol Testable Design & Test Integrated Syst TDT Grp POB 217 NL-7500 AE Enschede Netherlands

No fault found (NFF) is a major threat in extremely dependable high-end process node integrated systems, in e.g., avionics. One category of NFFs is the intermittent resistive fault (IRF), often originating from bad (e.g., via- or TSV-based) interconnections. this paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects can take e.g., one month, while the duration of the defect can be as short as 50 ns, thus to evoke and detect these faults is a huge scientific challenge. Two methods to detect short pulses induced by IRFs are proposed. To improve the task of maintenance of avionics and reduce the current high debugging costs, an on-chip data logging system with time stamp and stored environmental conditions is introduced. Finally, a hardware implementation of an IRF generator is presented.

关键词： Dependability reliability no faults found intermittent resistive faults evoking & detection of intermittent faults

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Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated circuits

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JOURNAL OF circuits systems AND COMPUTERS 2016年第3期25卷

作者： Azais, Florence David-Grignot, Stephane Latorre, Laurent Lefevre, Francois Univ Montpellier CNRS LIRMM 161 Rue Ada F-34095 Montpellier France NXP Semicond 2 Espl Anton Phillips F-14000 Caen France

this paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. the technique relies on 1-bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140nm technology occupies only 7,885 mu m(2), which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument.

关键词： Noise measurement phase noise analog/IF signals 1-bit acquisition digital signal processing built-in-self-test BIST test cost reduction

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Non-Cyclic design Space Exploration for ASIPs - Compiler-Centered Microprocessor design (CoMet)

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JOURNAL OF circuits systems AND COMPUTERS 2016年第3期25卷 1640012-1640012页

作者： Urban, Roberto Vierhaus, Heinrich T. Schoelzel, Mario Altmann, Enrico Seelig, Horst BTU Cottbus Senftenberg Postfach 101344 D-03046 Cottbus Germany IHP GmbH Technol Pk 25 D-15236 Frankfurt Oder Germany GED Elect Design GmbH Technol Pk 27 D-15236 Frankfurt Oder Germany

the CoMet approach on designing application specific instruction set processors (ASIPs) is targeting a non-cyclic design space exploration (DSE). the design process is driven by a step by step refinement of intermediate codes, known from compiler backends. In every step, the intermediate code can be simulated and profiled. Based on that profiling information, it can be further transformed to an optimized or refined intermediate code. the whole transformation process is implemented in a GUI-based design tool, whose main component is a configurable simulator for intermediate codes. It will be shown how the configurable intermediate code simulator is used and how the intermediate code transformation and the VHDL generation of the ASIP model will work in the CoMet tool.

关键词： ASIP design design space exploration CoMet intermediate codes compiler-driven design VHDL generation

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Analyzing Inconsistencies in UML/OCL Models

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JOURNAL OF circuits systems AND COMPUTERS 2016年第3期25卷

作者： Przigoda, Nils Wille, Robert Drechsler, Rolf Univ Bremen Grp Comp Architecture D-28359 Bremen Germany Johannes Kepler Univ Linz Inst Integrated Circuits A-4040 Linz Austria DFKI GmbH Cyber Phys Syst D-28359 Bremen Germany

Modeling languages such as the unified modeling language (UML) or the systems modeling language (SysML) in combination with constraint languages such as the object constraint language (OCL) allows for an abstract description of a system prior to its implementation. But the resulting system models can be highly non-trivial and, hence, errors in the descriptions can easily arise. In particular, too strong restrictions leading to an inconsistent model are common. Motivated by this, researchers and engineers developed methods for the validation and verification of given formal models. However, while these methods are efficient to detect the existence of an inconsistency, the designer is usually left alone to identify the reasons for it. In this contribution, we propose an automatic method which efficiently determines reasons explaining the contradiction in an inconsistent UML/OCL model. For this purpose, all constraints causing the contradiction are comprehensibly analyzed. By this, the designer is aided during the debugging of his/her model.

关键词： UML/OCL models inconsistent models contradiction analysis debugging

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