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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

共 683 条记录，以下是251-260 订阅

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Studying DAC Capacitor-Array Degradation in Charge-Redistribution SAR ADCs 17

Studying DAC Capacitor-Array Degradation in Charge-Redistrib...

引用

ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Khan, Muhammad Aamir Kerkhoff, Hans G. Univ Twente CTIT Testable Design & Test Integrated Syst TDT Grp NL-7500 AE Enschede Netherlands

ISBN: (纸本)9781479945580

In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study the aging effects in static and dynamic performance parameters. A comparison of results from the degradation in the buffer and comparator with reference to the degradation in the capacitor array has also been conducted. Most of the static and dynamic performance parameters are severely affected by the DAC capacitor-array degradations. Whereas, in case of the buffer and comparator degradations, only offset from the static performance parameters and all of the dynamic performance parameters are severely affected. the simulation results can be used in advance by electronic designers to come to a more reliable design, especially in aging-critical technology nodes.

关键词： degradation modelling analysis charge-redistribution SAR ADC sensitivity analysis DAC capacitor-array degradation dependable design

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Lower Bounds of the Size of Shared Structurally Synthesized BDDs 17

Lower Bounds of the Size of Shared Structurally Synthesized ...

引用

ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ubar, Raimund Mironov, Dmitri Tallinn Univ Technol EE-19086 Tallinn Estonia

ISBN: (纸本)9781479945580

A novel type of BDDs called Shared Structurally Synthesized BDDs (S3BDD) is presented as an extension of the SSBDDs, and a method is given to minimize the size of the model. As in case of SSBDDs, the S3BDDs have linear complexity compared to the size of the logic circuit they represent, and they are characterized by the property of one-to-one mapping between the nodes of graphs and signal paths in the circuit. Minimization of S3BDDs makes it possible to get higher rates in fault collapsing, and to speed-up logic simulation as a main tool in delay analysis, fault reasoning and test generation. A lower bound is developed for the size of S3BDDs to evaluate the results of S3BDD synthesis, and it is shown that this bound can be reached rather closely by a straightforward method. Experimental results demonstrate that the S3BDDs represent the most compact BDD based model representing the structure of the digital circuits, which has in average 1.5 times less nodes than the SSBDDs.

关键词： digital circuits logic models and simulation Binary Decision Diagrams Shared Structurally Synthesized BDDs lower bounds

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Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic 17

Online Test Vector Insertion: A Concurrent Built-In Self-Tes...

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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Maier, Juergen Steininger, Andreas Vienna Univ Technol Inst Comp Engn Vienna Austria

ISBN: (纸本)9781479945580

Complementing concurrent checking with online testing is crucial for preventing fault accumulation in fault-tolerant systems with long mission times. While implementing a non-intrusive online test is cumbersome in a synchronous environment, this task becomes even more challenging in asynchronous designs. the latter receive increasing attention, mainly due to their elastic timing behaviour;however the issues related with their testing remain a key obstacle for their wide adoption. In this paper we present a novel approach for testing of asynchronous circuits that leverages the redundancy present in the conventional 4-phase protocol for implementing a fully transparent and fully concurrent test procedure. the key idea is to use the protocol's unproductive NULL phase for processing test vectors, thus effectively interleaving the incoming 4-phase data stream with a test data stream in a 2-phase fashion. We present implementation templates for the fundamental building blocks required and give a proof-of-concept by an example application that also serves as a platform for evaluating the overheads of our solution which turn out to be moderate.

关键词： asynchronous logic on line detection Built-in self test mission time asynchronous circuits observational data Testing Procedures Building blocks Asynchronous

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design Methodology of Configurable High Performance Packet Parser for FPGA 17

Design Methodology of Configurable High Performance Packet P...

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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Pus, Viktor Kekely, Lukas Korenek, Jan CESNET Ale Zikova 4 CZ-16000 Prague Czech Republic Brno Univ Technol IT4 Innovat Ctr Excellence Fac Informat Technol CZ-61266 Brno Czech Republic

ISBN: (纸本)9781479945580

Packet parsing is among basic operations that are performed at all points of a network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules. However, high-speed parsers often use a significant amount of hardware resources. We propose a novel architecture of a pipelined packet parser for FPGA, which offers low latency in addition to high throughput (over 100 Gb/s). Moreover, the latency, throughput and chip area can be finely tuned to fit the needs of a particular application. the parser is hand-optimized thanks to a direct implementation in VHDL, yet the structure is uniform and easily extensible for new protocols.

关键词： Packet Parsing Latency FPGA

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Numerical and theoretical Analysis on Voltage and Time Domain Dynamic Range of scaled CMOS circuits. 17

Numerical and Theoretical Analysis on Voltage and Time Domai...

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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Muriithi, Kevin Ngari Nakura, Toru Asada, Kunihiro Univ Tokyo Dept Elect Engn & Informat Syst Tokyo 1138654 Japan Univ Tokyo VLSI Design & Educ Ctr VDEC Tokyo Japan

ISBN: (纸本)9781479945580

It is believed that the time-domain resolution of a digital signal edge transition is superior to the voltage resolution of an analog signal in advanced CMOS processes[1], [2]. the reasoning behind this is that operating voltage has been reducing, making the signal more vulnerable to noise power due to scaling. On the other hand, in time domain, scaling has resulted to increase in frequency and therefore design of faster circuits, while also contributing to reduction of jitter. However, this is a concept that has not yet been quantitatively examined. this paper aims at verifying the effectiveness of the time-domain circuits over voltage-domain circuits in terms of their dynamic range performances by simulations as well as by theoretical analysis, especially in the scaled nano-meter processes. It has been shown that for a given technology the time domain dynamic range is superior to the voltage domain dynamic range by a factor of (omega(T) / B)(2) where omega(T) is the unity gain frequency and B is the bandwidth.

关键词： TIME-DOMAIN theoretical analysis Dynamic range VOLTAGE Electric circuits unity gain ANALOG SIGNALS noise power operating voltage Numerical Complementary Metal Oxide Semiconductor Scale formation nanometer CMOS circuits CMOS integrated circuits linear CMOS circuits

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A design of an Area-Efficient 10-GHz Phase-Locked Loop for Source-Synchronous, Multi-Channel Links in 90-nm CMOS Technology 17

A Design of an Area-Efficient 10-GHz Phase-Locked Loop for S...

引用

ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Bae, Woorham Jeong, Deog-Kyoon Yoo, Byoung-Joo Seoul Natl Univ Dept Elect & Comp Engn Interuniv Semicond Res Ctr Seoul South Korea Samsung Elect Syst LSI Div Hwasong North Korea

ISBN: (纸本)9781479945580

this paper presents a design of an area-efficient 10-GHz PLL for source-synchronous, multi-channel applications. To be applied in the multi-channel application, the proposed PLL is implemented without use of any high-cost inductor to minimize silicon area while achieving 10-GHz operation frequency. A modified CML type ring-VCO is used to make the VCO outputs have consistent signal amplitude. the proposed PLL is fabricated in 90-nm low-power CMOS technology. the prototype IC occupies 0.075mm(2) of active area and dissipates 87.6-mW power from 1.2-V supply including a 10-GHz clock driver.

关键词： Phase-locked loop current-mode logic frequency divider voltage-controlled oscillator

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Test-Data Compression with Low Number of Channels and Short Test Time 17

Test-Data Compression with Low Number of Channels and Short ...

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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Novak, Ondrej Jenicek, Jiri Rozkovec, Martin Tech Univ Liberec Inst Informat Technol & Elect Liberec Czech Republic

ISBN: (纸本)9781479945580

the paper describes a modified Smart BIST methodology that provides test data volume compression. the test equipment is easily applicable because it is based on the standard scan methodology. the method is based on continuous LFSR reseeding decompression that is used in such a way that it enables lockout escaping within a small number of clock cycles. It requires a separate controlling of the LFSR decompressor and the scan chain clock inputs. We propose a modified LFSR with state skipping for the pattern decompression that does not require a phase shifter and saves hardware. A pattern encoding algorithm minimizing the number of clock cycles of the decompressor needed for decoding test patterns is also proposed. the parameters can be tuned in such a way that the method provides similar data magnitude reduction and decompressor hardware overhead as other test compression methods but it substantially reduces test time, number of tester channels and hardware overhead. Experimental results of benchmark circuit testing show that the modified Smart BIST methodology provides unreduced test coverage, low hardware overhead and short test sequences.

关键词： design for testability (DFT) linear finite state machines manufacturing test test application time reduction test data volume compression

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Optimizing DD-based Synthesis of Reversible circuits using Negative Control Lines 17

Optimizing DD-based Synthesis of Reversible Circuits using N...

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ieee 17th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Schoenborn, Eleonora Datta, Kamalika Wille, Robert Sengupta, Indranil Rahaman, Hafizur Drechsler, Rolf Univ Bremen Inst Comp Sci D-28359 Bremen Germany Bengal Engn Sci Univ Dept Informat Technol Sibpur 711103 India DFKI GmbH Cyber Phys Syst D-28359 Bremen Germany Indian Inst Technol Dept Comp Sci & Engn Kharagpur 721301 West Bengal India

ISBN: (纸本)9781479945580

Synthesis of reversible circuits has attracted the attention of many researchers. In particular, approaches based on Decision Diagrams (DDs) have been shown beneficial since they enable the realization of corresponding circuits for large functions. However, all existing approaches rely on a gate library composed of positive control lines only. Recently, it has been shown that the additional use of negative control lines enables significant reductions of the respective circuit costs. In this paper, we aim for exploiting this potential. To this end, two complementary schemes are investigated. First, a post-synthesis optimization that exploits the power of negative control lines is utilized to optimize the circuits generated by previously proposed DD-based methods. Second, negative control lines are explicitly considered during synthesis. Experimental results demonstrate that the proposed approaches result in a significant reduction with respect to gate count as well as quantum costs.

关键词： Control lines Electric circuits reciprocal circuit synthesis Negative

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Notice of Violation of ieee Publication Principles: Super-scale architecture enhancement of LEON3 core for DSP application

Notice of Violation of IEEE Publication Principles: Super-sc...

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International symposium on VLSI design and Test (VDAT)

作者： Jagrat Mehta Anand Darji T V S Ram Rajat Arora Electronics and Communication Engineering Department Charusat University Gujarat India Department of Electronics Engineering SVNIT Surat Gujarat India ISRO Space Application Centre Ahmedabad Gujarat India

Notice of Violation of ieee Publication Principles "Super-Scale Architecture Enhancement of LEON3 Core for DSP Application" By Jagrat Mehta, Anand Darji, TVS Ram, Rajat Arora in the Proceedings of the 19th International symposium on VLSI design and Test (VDAT), June 2015 After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of ieee's Publication Principles. this paper contains substantial duplicate text from the paper cited below. the original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article: "Enhanced LEON3 Core for Superscalar Processing" by Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz in the Proceedings of the 12th International symposium on design and diagnostics of electronic circuits & systems, (DDECS), April 2009, pp. 238-241 there are two main directions in the development of modern microprocessor architectures used for System on Chip: low Power consumption and high performance. the paper presents the method for enhancing LEON3 processor IP core with superscalar ability for high-performance and low-power systems. As compared to the original LEON3 IP core, the proposed super scalar design executes is up to two instructions per cycle with only one third area increase. Application to perform FFT/IFFT is developed and tested using enhanced architecture of LEON3 IP core for superscalar processing. Performance enhancement of LEON3 core is also compared with Very Long Instruction Word (VLIW) processor and Silicon labs application note. the enhanced SoC is synthesized and implemented on Actel FPGA ProASIC3E. the area, power and timing comparison is shown. Approximately 33% enhanc

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symposium committees

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ieee design and diagnostics of electronic circuits and systems (DDECS)

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