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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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A 120V high voltage DAC array for a tunable antenna in communication system

A 120V high voltage DAC array for a tunable antenna in commu...

引用

ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Jing Ning Klaus Hofmann Integrated Electronic System Lab TU Darmstadt Darmstadt Germany

this paper presents a integrated high voltage digital-to-analog converter array, which is designed by using a 0.35μm high voltage CMOS technology(AMS H35), and can be applied in high voltage applications up to 120V. the DAC array has 16 high voltage DACs controlled by a digital controller on chip. To fulfil the requirement of communication system with reconfigurable antenna implemented using materials which have voltage dependent capacitance, the DACs are designed to have 8 bits of resolution. In order to improve the accuracy and decrease the required area, each independent DAC is implemented by a low voltage DAC and a high voltage amplifier for boosting the controllable output voltage. Since the current consumption from the high voltage power supply is only 1.28mA, it is possible to be powered by a charge pump which generates high voltage power supply from a battery. the proposed HV DAC array can drive up to 16 individual channels of antenna array with different voltages from 0V to 120V. It will greatly reduce the complexity and cost of mobile applications required high voltage. the feasibility is proved by post-simulation result.

关键词： Arrays Transistors Antenna arrays Low voltage Voltage control Power supplies Charge pumps

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Mismatch effects and their correction in large area ASICs

Mismatch effects and their correction in large area ASICs

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ieee design and diagnostics of electronic circuits and systems (DDECS)

作者： Piotr Maj Department of Measurement and Electronics AGH University of Science and Electronics Krakow Poland

Hybrid pixel detectors working in single photon counting mode are very attractive solution for new experiments as their functionality increases and the single pixel size is getting smaller. this is possible due to new deep sub-micron technologies, which allows making smaller devices. However, making smaller devices has drawbacks, one of which is that matching of smaller transistors decreases, resulting in higher offset spread of DC operating points in channels. Having large area pixel detector containing over 20.000 channels an efficient correction circuit is required in each channel allowing effective trimming of the entire matrix including small percentage of exceptional pixels. If the readout circuit contains a discriminator, different correction circuits are used for minimization of the mismatch effect usually at the discriminator input. As the pixel size is minimized correction DACs quality is often degraded and therefore it is not only non-linear but also likely non-monotonic. the large multi-thousand channel systems requires fast calculation of the correction DACs values in order to make the whole system useful. the correction scheme implemented in the large area hybrid pixel detector readout circuit containing 23552 pixels with a size of 100um × 100um each will be presented together with adequate measurements and applied correction algorithms.

关键词： Detectors Integrated circuits Noise Photonics threshold voltage Prototypes Noise measurement

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Numerical method for DC fault analysis simplification and simulation time reduction

Numerical method for DC fault analysis simplification and si...

引用

ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Brenkus, Juraj Stopjakova, Viera Gyepes, Gabor Slovak Univ Technol Bratislava Dept IC Design & Test Inst Elect & Photon Bratislava Slovakia

ISBN: (纸本)9781467361361;9781467361354

this paper presents a numerical approach to DC fault analysis of analog circuits that improves the total computational time and reduces the total complexity of such analysis. the reduction is achieved by utilization of calculus that can substitute conventional simulations and thus, significantly reducing computational time. A detailed description of the approach including its mathematical background is presented. Accuracy and time efficiency are demonstrated on a test circuit.

关键词： resistance analog circuit fault analysis test simulation

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Proton Beam Characterization at Oslo Cyclotron Laboratory for Radiation Testing of electronic Devices

Proton Beam Characterization at Oslo Cyclotron Laboratory fo...

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Hasanbegovic, Amir Aunet, Snorre Univ Oslo Dept Informat PB 1080 Blindern N-0316 Oslo Norway Dept Elect & Telecommun N-7491 Trondheim Norway

ISBN: (纸本)9781467361361;9781467361354

Proton beam characterization was performed at the Oslo Cyclotron Laboratory (OCL) in order to evaluate the beam properties and asses its usability for radiation testing of electronic devices. the characterization was performed with the aim of establishing good guidelines for reliable radiation tolerance testing at the OCL. A dosimetry measurement and calibration setup is proposed as well as a beam-to-target alignment and beam profile measurement setup. the beam characterization was performed using 30 MeV protons.

关键词： Cyclotrons

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Improved design of the Uninterruptable Power Supply Unit for Powering of Network Devices

Improved Design of the Uninterruptable Power Supply Unit for...

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Pospisilik, Martin Neumann, Petr Tomas Bata Univ Zlin Fac Appl Informat Zlin Czech Republic

ISBN: (纸本)9781467361361;9781467361354

Paper describes suggestions on the improvement of the common On-line structure of the uninterruptable power supply units used for powering of network devices. According to these suggestions a prototype circuit able to deliver the output power up to 150 W was constructed. the topology was optimized in order maximum efficiency was achieved when the output is fed by an accumulator in order the operating time was as long as possible.

关键词： Uninterruptable Power Supply Network Devices Power on Ethernet Lead-acid Accumulators

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Efficient Automated Speedpath Debugging

Efficient Automated Speedpath Debugging

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Dehbashi, Mehdi Fey, Goerschwin Univ Bremen Inst Comp Sci D-28359 Bremen Germany

ISBN: (纸本)9781467361361;9781467361354

Speedpath diagnosis is one of the major challenges in designing high-performance Very-Large-Scale Integrated (VLSI) circuits due to timing variations caused by process variations and environmental effects. In this paper, an efficient approach to automate speedpath debugging is presented. the approach relies on converting the timing behavior of a circuit and its corresponding timing variations into functional domain. Afterwards, a SAT-based debug engine is utilized to extract potential failing speedpaths. the experimental results on ISCAS' 85 and ISCAS'89 benchmark suites show that our approach achieves a 63% decrease in the size of model resulting in 54% decrease in the debugging time compared to previous work while having a high diagnosis accuracy.

关键词： Timing circuits

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Digital Methods of Offset Compensation in 90nm CMOS Operational Amplifiers

Digital Methods of Offset Compensation in 90nm CMOS Operatio...

引用

ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Nagy, Gabriel Arbet, Daniel Stopjakova, Viera Slovak Univ Technol Bratislava Dept IC Design & Test Inst Elect & Photon Bratislava Slovakia

ISBN: (纸本)9781467361361;9781467361354

this paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ladder, one using successive approximation register (SAR) and the other employing a simple counter, were compared. Furthermore, a correction circuit was proposed and used to form the mean offset voltage and increase the probability that its value after trimming process will be near zero. Finally, achieved results and improvements are discussed.

关键词： input offset compensation operational amplifier 90nm CMOS digital calibration analog circuits

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Interpolation-Based Model Checking for Efficient Incremental Analysis of Software

Interpolation-Based Model Checking for Efficient Incremental...

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Fedyukovich, Grigory Hyvaerinen, Antti E. J. Sharygina, Natasha Univ Lugano Fac Informat Via Guiseppe Buffi 13 CH-6904 Lugano Switzerland

ISBN: (纸本)9781467361361;9781467361354

Verification based on model checking has recently obtained an important role in certain software engineering tasks, such as developing operating system device drivers. this extended abstract discusses how model checking can be made more efficient by using the structure from program function calls. We use this idea in two orthogonal ways, both of which fundamentally depend on automatically summarizing the relevant behavior of the function calls based on an earlier verification. the first approach assumes a piece of software needs to be verified with respect to a set of properties, whereas the second approach considers a case where an early version of a software has been verified but needs to be re-verified after an upgrade. these techniques have been implemented in tools FunFrog and eVolCheck for verifying C programs. Both of them have been tested on a range of academic and industrial benchmarks, and provide in many cases an order of magnitude speed-up with respect to the baseline. they seem to scale to programs with thousands of lines of code.

关键词： Model checking

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On design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time systems

On Design of Priority-Driven Load-Adaptive Monitoring-Based ...

引用

ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Strnadel, Josef Brno Univ Technol Fac Informat Technol Ctr Excellence IT4Innovat CS-61090 Brno Czech Republic

ISBN: (纸本)9781467361361;9781467361354

the paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. the load is monitored on basis of special low-overhead signals produced by the system for this purpose. the hardware is designed to pre-process all interrupts before they arrive to the system. then, the hardware is able to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks, overheads and limits related to the realization are presented in this paper.

关键词： Real time systems

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Power Analysis Methodology for Secure circuits

Power Analysis Methodology for Secure Circuits

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Gomina, Kamil Rigaud, Jean-Baptiste Gendrier, Philippe Candelier, Philippe Tria, Assia STMicroelectronics 850 Rue Jean Monnet F-38926 Crolles France Ecole Natl Super Mines Dept Syst Architectures Securisees SAS F-42023 St Etienne France

ISBN: (纸本)9781467361361;9781467361354

A study on power consumption of a digital synchronous circuit in advanced CMOS technology is performed. these technologies target low power applications allowing accurate power analysis. A model of power signature is developed to identify data related consumption using current consumption and power delivery network capacitance at design phase. In addition to digital power characterization tool, device junction capacitance is extracted and used to provide an accurate power signature. Simulations are compared to experimental traces on a synchronous digital circuit to validate the approach. this model can also be used for complex analog/digital circuit. Finally two countermeasures masking and decoupling capacitance flattening are analyzed with our methodology in early design phase allowing to anticipate silicon tests.

关键词： Capacitance

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