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检索条件"任意字段=13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems"

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Fault-based Attacks on Cryptographic Hardware

Fault-based Attacks on Cryptographic Hardware

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Polian, Ilia Kreuzer, Martin Univ Passau Fac Comp Sci & Math D-94032 Passau Germany

ISBN: (纸本)9781467361361;9781467361354

Mobile and embedded systems increasingly process sensitive data, ranging from personal information including health records or financial transactions to parameters of technical systems such as car engines. Cryptographic circuits are employed to protect these data from unauthorized access and manipulation. Fault-based attacks are a relatively new threat to system integrity. they circumvent the protection by inducing faults into the hardware implementation of cryptographic functions, thus affecting encryption and/or decryption in a controlled way. By doing so, the attacker obtains supplementary information that she can utilize during cryptanalysis to derive protected data, such as secret keys. In the recent years, a large number of fault-based attacks and countermeasures to protect cryptographic circuits against them have been developed. However, isolated techniques for each individual attack are no longer sufficient, and a generic protective strategy is lacking.

关键词： system integrity unauthorized access patient information system Computer hardware Mobile AUTOMOTIVE ENGINES Electric circuits cryptography cryptographic function Sensitive data Decryption

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An Indirect Technique for Estimating Reliability of Analog and Mixed-Signal systems during Operational Life

An Indirect Technique for Estimating Reliability of Analog a...

引用

ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Khan, Muhammad Aamir Kerkhoff, Hans G. Univ Twente Testable Design & Test Integrated Syst TDT Grp Ctr Telemat & Informat Technol CTIT NL-7500 AE Enschede Netherlands

ISBN: (纸本)9781467361361;9781467361354

Reliability of electronic systems has been thoroughly investigated in literature and a number of analytical approaches at the design stage are already available via examination of the circuit-level reliability effects based on device-level models. Reliability estimation during operational life of an electronic system still lacks a solution especially for analog and mixed signal systems. the current work will present a novel technique for indirectly estimating reliability during operational life of an electronic system. Reliability simulations during the design stage of a potential critical performance parameter, sensitive to aging effects, over a range of input-stress voltages and working-stress temperatures have been used to generate a set of degradation values per unit time. these values are then used at the system level to estimate the degradation in that particular performance parameter and hence system reliability by regularly monitoring the input-stress voltages and working-stress temperatures. the simulation results conducted for an example target system in a LabVIEW environment show that the proposed technique is viable.

关键词： reliability input signal monitoring temperature monitoring time before failure offset voltage

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Composing Data-driven circuits Using Handshake in the Clock-Synchronous Domain

Composing Data-driven Circuits Using Handshake in the Clock-...

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Sykora, Jaroslav ASCR Inst Informat Theory & Automat UTIA Prague Czech Republic

ISBN: (纸本)9781467361361;9781467361354

We present a technique for modelling and synthesis of fine-grained data-driven circuits in the clock-synchronous hardware, such as the field programmable gate arrays (FPGA), called the Flow-Transfer Level (FTL). the distinguishing property of the FTL technique is that it does not rely on FIFO queues to handle flow synchronization between the components (called operators). the communication channels, called pipes, employ conceptually a two-state handshake protocol. the handshake behaviour of each operator is defined logically using dependency subgraphs that are symmetrical for producers and consumers. the original data-flow netlist of operators is transformed into a global control dependency graph. Cycles in dependency graphs are allowed as long as they do not constitute real data dependencies but only dependencies in promises of handshake completions. A method is given that recursively eliminates these cycles. We demonstrate the feasibility of the approach in a prototype compiler that transforms an FTL netlist into a synthesizable VHDL code. A comparison to a manual RTL VHDL design shows that our technique is very lightweight, yet it has a potential of increasing the design abstraction level.

关键词： Clocks

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Analysis and Comparison of Functional Verification and ATPG for Testing design Reliability

Analysis and Comparison of Functional Verification and ATPG ...

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Simkova, Marcela Kotasek, Zdenek Bolchini, Cristiana Brno Univ Technol Fac Informat Technol CS-61090 Brno Czech Republic Politecn Milan Dip Elettr Informaz Bioingn Milan Italy

ISBN: (纸本)9781467361361;9781467361354

As the complexity of current hardware systems rises, it is challenging to harden these systems against faults and to complete their verification and manufacturing test. Not only that verification and testing take a considerable amount of time but the number of design errors, faults and manufacturing defects increases with the rising complexity as well. In this paper we performed a detailed analysis of two approaches devoted to generation of input test vectors with respect to detection of stuck-at faults: the first one is based on classical Automatic Test Pattern Generation, the second one on Constrained-random Stimulus Generation. We evaluated their qualities as well as their drawbacks and introduced ideas about their combination in order to create a new promising approach for testing reliable systems.

关键词： Quality control

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design of an S-band 0.35 μm AlGaN/GaN LNA using Cascode Topology

Design of an S-band 0.35 μm AlGaN/GaN LNA using Cascode Top...

引用

ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Kao, H. L. Yeh, C. S. Cho, C. L. Wang, B. W. Lee, P. C. Wei, B. H. Chiu, H. C. Chang Gung Univ Dept Elect Engn Tao Yuan Taiwan

ISBN: (纸本)9781467361361;9781467361354

this paper presents an S-band low noise amplifier that uses a two-stage configuration. the first stage has a cascode topology and the second stage has a RC feedback topology. the S-band LNA uses a 0.35 mu m AlGaN/GaN HEMT on a Si-substrate. the results show a maximum gain of 17.2 dB, a minimum noise figure of 2.9 dB and an input/output return loss greater than 9.2/10 dB. the input IIP3 at 2.8 GHz is 2.5 dBm and the unit consumes 230 mW of power.

关键词： LNA S-band AlGaN/GaN HEMT on Si

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Energy-Aware Software Development for Embedded systems in HW/SW Co-design

Energy-Aware Software Development for Embedded Systems in HW...

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Ehrlich, Paul Radke, Stephan Fraunhofer IIS Design Automat Div EAS Dresden Germany

ISBN: (纸本)9781467361361;9781467361354

Power constrains are becoming increasingly important for embedded systems, especially when considering mobile applications. these systems are characterized by the presence of a dedicated processor running application-specific software. Current approaches only focus on power optimization in one design domain, such as the hardware or the software one. However, to meet the tight power constrains, both have to be investigated in relation. this paper proposes a novel approach to support the software developing process which takes this relation into account. Based on hardware/software co-simulation, the power consumption of the hardware is annotated to the corresponding source code. Hence, the consumption of the system is directly visible during software refinements of the microcontroller. After each refinement cycle, an overall power optimization can be accomplished. the approach is applied to an example system which comprises the embedded software of a MSP430 microcontroller and its controlled external peripherals. Using the example, the potential of the approach is discussed. Moreover, the power annotation process is defined and the data exchange formats are specified. therefore, the approach is also applicable to any other controller type.

关键词： Power-Analysis Embedded systems design Hardware/Software Co-design Power System Simulation

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Yield-Oriented Energy and Performance Model for Subthreshold circuits with Vth Variations

Yield-Oriented Energy and Performance Model for Subthreshold...

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Berge, Hans Kristian Otnes Aunet, Snorre Univ Oslo Dept Informat N-0316 Oslo Norway Norwegian Univ Sci & Technol Dept Elect & Telecommun Trondheim Norway

ISBN: (纸本)9781467361361;9781467361354

We present a method to analyze the minimum energy point of subthreshold logic circuits, taking into account the effect of gate sizing and the transistor threshold voltage variability. With respect to a target yield, technology and circuit parameters this method can give estimates of optimal choices for supply voltage and gate sizing, as well as serve as a tool for design space exploration and technology comparision. We apply this modeling technique to a 90 nm technology, and draw contour plots of the design space. these plots indicate that larger than minimum size gates may be required to achieve minimum energy operation in the subthreshold domain. Optimal voltages range from about 350 mV to 550 mV, depending on the switching activity of the circuit. In the appendix we also give a method of approximating the sum of iid. log-normal RVs, which is used to analyze the timing performance of gates in series.

关键词： gates subthreshold Logic circuits PERFORMANCE MODELING Space Exploration supply voltage threshold voltage Appendix SIZING contour Energy sources Electric circuits

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On the Feasibility of Combining On-Line-Test and Self Repair for Logic circuits

On the Feasibility of Combining On-Line-Test and Self Repair...

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Koal, Tobias Ulbricht, Markus Engelke, Piet Vierhaus, Heinrich. T. Brandenburg Tech Univ Cottbus Cottbus Germany Infineon Technol AG Neubiberg Germany

ISBN: (纸本)9781467361361;9781467361354

Integrated circuits and systems implemented by using nano-technologies show a combination of known and new faults effects, which affect their reliability and their operational life time, specifically in safety-critical applications. Transient fault effects such as single and multiple event upsets (SEUs and MEUs) require fast error detection and compensation. Permanent faults may occur due to early life time failures on one side and stress-induced rapid aging on the other hand. they need to be compensated by repair technologies, preferably using "fresh" resources for the replacement of faulty functional units. As self repair is typically not a fast process and requires extra time while the system is off-line, on-line fault compensation must also catch and handle permanent faults that occur during "hot" operation. If on-line-test and error compensation on one side and repair technologies on the other hand are implemented independently, the resulting overhead in redundant circuitry becomes prohibitively high. In the following paper we therefore introduce a new concept of logic design which can meet the essential demands at reasonable cost using a flexible allocation of redundancy.

关键词： Error compensation

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design of Stochastic Viterbi Decoders for Convolutional Codes

Design of Stochastic Viterbi Decoders for Convolutional Code...

引用

ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Chen, Te-Hsuan Hayes, John P. Univ Michigan Dept Elect Engn & Comp Sci Adv Comp Architecture Lab Ann Arbor MI 48109 USA

ISBN: (纸本)9781467361361;9781467361354

the Viterbi algorithm is widely used to decode convolutional codes. We present an unconventional approach to Viterbi decoder design based on stochastic computing (SC) which represents data by random bit-streams that can be interpreted as probabilities. Stochastic circuits allow many decoding functions to be implemented by simple hardware;e.g., multi-bit multiplication can be realized by an AND gate. SC is also highly error-tolerant since a soft error (bit-flip) has little impact on a SC number's value. It also allows decoding precision to be traded for decoding speed. We design two SC-based Viterbi decoders and also a hybrid binary-SC design;the latter uses SC for arithmetic calculations, but not for storing numbers. the proposed designs are compared with a binary (non-SC) decoder using a standard (7,1/2) convolutional code. the SC designs are found to be more tolerant of soft errors in the decoder than the binary design, and more capable of supporting some useful trade-offs among area cost, data rate, precision, and bit-error rate.

关键词： Stochastic computing Stochastic logic design Viterbi decoders Convolutional codes

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A New Method for Correcting Time and Soft Errors in Combinational circuits

A New Method for Correcting Time and Soft Errors in Combinat...

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ieee 16th International symposium on design and diagnostics of electronic circuits and systems (DDECS)

作者： Sogomonyan, Egor S. Weidling, Stefan Goessel, Michael Univ Potsdam Dept Comp Sci D-14482 Potsdam Germany

ISBN: (纸本)9781467361361;9781467361354

In this paper a simple method for fault tolerance with respect to transient or soft errors in the combinational part of sequential circuits is investigated. the memory elements of the sequential circuits are fault-tolerant master-slave-flip-flops. For correcting errors in the combinational part instead of error-correcting codes (ECCs) much simpler error-detecting codes can be used. An error detection signal indicating an error in a combinational part of the circuit blocks the clock signal in the second half of the clock cycle with the result that the previous correct state values of all the slave latches are preserved as long as the transient error (of any duration) stays in the combinational circuit. As soon as the transient error disappears, the system can continue to work from a correct state immediately;no complicated restart of the system is necessary. the system has only to stop for the duration of the transient error. the necessary time delay of the error signal determined by the error-detecting code limits the length of the clock cycle for which the proposed method is applicable. therefore simple error-detecting codes such as parity codes, split-parity codes and duplication codes should be used. For the mentioned codes the time delay and the error detection probabilities which correspond to the error correction probabilities of this method are determined for benchmark circuits experimentally.

关键词： Timing circuits

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